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    EP2C8 Price and Stock

    Intel Corporation EP2C8F256C7N

    IC FPGA 182 I/O 256FBGA
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    DigiKey EP2C8F256C7N Tray 516 1
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    Intel Corporation EP2C8Q208C8N

    IC FPGA 138 I/O 208QFP
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    DigiKey EP2C8Q208C8N Tray 496 1
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    Chip 1 Exchange EP2C8Q208C8N 1,098
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    Intel Corporation EP2C8Q208C7N

    IC FPGA 138 I/O 208QFP
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    DigiKey EP2C8Q208C7N Tray 305 1
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    Verical EP2C8Q208C7N 72 72
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    Arrow Electronics EP2C8Q208C7N 72 26 Weeks 96
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    TME EP2C8Q208C7N 1
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    Intel Corporation EP2C8T144C8N

    IC FPGA 85 I/O 144TQFP
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    DigiKey EP2C8T144C8N Tray 195 1
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    Intel Corporation EP2C8T144I8N

    IC FPGA 85 I/O 144TQFP
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    DigiKey EP2C8T144I8N Tray 184 1
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    TME EP2C8T144I8N 1
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    EP2C8 Datasheets (28)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EP2C8 Altera SECTION IV. I/O STANDARDS Scan PDF
    EP2C8AF256A7N Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 182 I/O 256FBGA Original PDF
    EP2C8AF256I8N Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8AF256I8N Intel Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC CYCLONE II FPGA 8K 256FBGA Original PDF
    EP2C8AF256I8NES Altera Cyclone™ II FPGAs; 256 pin FBGA; -40 to 100°C Original PDF
    EP2C8F256C6 Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256C6N Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256C7 Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256C7N Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256C8 Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256C8N Altera Accessories, Cyclone II devices Original PDF
    EP2C8F256C8N Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256I8 Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8F256I8N Altera Cyclone II FPGA 8K FBGA-256 Original PDF
    EP2C8Q208C7 Altera Cyclone II FPGA 8K PQFP-208 Original PDF
    EP2C8Q208C7N Altera Cyclone II FPGA 8K PQFP-208 Original PDF
    EP2C8Q208C8 Altera Cyclone II FPGA 8K PQFP-208 Original PDF
    EP2C8Q208C8N Altera Cyclone II FPGA 8K PQFP-208 Original PDF
    EP2C8Q208I8 Altera Cyclone II FPGA 8K PQFP-208 Original PDF
    EP2C8Q208I8N Altera Cyclone II FPGA 8K PQFP-208 Original PDF

    EP2C8 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    diode B4 discription

    Abstract: DDR2 pin out F256
    Text: Cyclone II EP2C8 & EP2C8A Device Pin-Out PT-EP2C8-1.9 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or


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    p14 115

    Abstract: 200-a5 F256 B3207 Cyclone II FPGA EP2C8
    Text: Pin Information for the Cyclone II EP2C8 & EP2C8A Devices Version 1.8 Notes 1 , (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1


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    p14 115

    Abstract: F256 p14115 EP2C8
    Text: Pin Information for the Cyclone II EP2C8 & EP2C8A Devices Version 1.6 Note 1 , (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1


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    5M80ZT100

    Abstract: 5M570ZM100 5M2210ZF256 5M160ZE64 5m240Zt100 5M1270ZF324 5m570ZT144 EP4CE15F17 5M40ZE64A5 5M1270ZT
    Text: The Automotive-Grade Device Handbook The Automotive-Grade Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com AUT5V1-2.0 Document last updated for Altera Complete Design Suite version: Document publication date: 11.0 May 2011 Subscribe 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.


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    PCI-M32

    Abstract: verilog code for MII phy interface
    Text: Network Interface Features − Support for 10/100 Mbps data transfer rate MAC-PCI Ethernet MAC Controller with PCI Host Interface Megafunction − Media Independent Interface MII for 10/100 Mbps operation − Automated MII Management interface Data Link Layer Functionality


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    32-bit PCI-M32) PCI-M32 verilog code for MII phy interface PDF

    intel 8051 Arithmetic and Logic Unit -ALU

    Abstract: Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 ASM51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051
    Text:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Megafunction An economical, entry-point, fixed-configuration megafunction that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.


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    R8051XC-EP 8051-Compatible 8051-like ASM51 80C31, R8051XC-EP 80C51) intel 8051 Arithmetic and Logic Unit -ALU Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051 PDF

    Untitled

    Abstract: No abstract text available
    Text:  Interfaces directly to Mobile and SDR-SDRAMCTRL Single Data Rate Mobile SDRAM Controller Megafunction ordinary Single Data Rate SDR SDRAM chips and registered/unbuffered DIMMS  Supports address space up to 2G (230 words) and – one to eight chip selects,


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    EPCS16

    Abstract: epcs128 1064V
    Text: 1. Altera Configuration Devices CF52001-2.4 Introduction During device operation, Altera FPGAs store configuration data in SRAM cells. Because SRAM memory is volatile, the SRAM cells must be loaded with configuration data each time the device powers up. You can configure Stratix® series, Cyclone®


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    CF52001-2 EPC16, 20ction. EPCS16 EPCS64 epcs128 1064V PDF

    CII51001-1

    Abstract: CII51002-1 EP2C20 EP2C35 EP2C50 SSTL-18
    Text: Section I. Cyclone II Device Family Data Sheet This section provides provides information for board layout designers to successfully layout their boards for Cyclone II devices. It contains the required PCB layout guidelines, device pin tables, and package


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    320x240 VHDL

    Abstract: sharp 640x240 lcd LCD controller 240x320 DVI VHDL DB9000 fpga TFT altera DB9000AVLN Cyclone TFT DVI verilog DB9000 tft
    Text: Digital Blocks DB9000AVLN Semiconductor IP Avalon Bus TFT LCD Controller General Description The Digital Blocks DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus to a TFT LCD panel. In an Altera FPGA, typically, the microprocessor is a NIOS II processor and frame buffer


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    DB9000AVLN DB9000AVLN DB9000AVLN-DS-V1 320x240 VHDL sharp 640x240 lcd LCD controller 240x320 DVI VHDL DB9000 fpga TFT altera Cyclone TFT DVI verilog DB9000 tft PDF

    PCN1205

    Abstract: EP3C120F780I7N EP4CE30F29I8LN EP4CGX50CF23C8 EP2SGX125GF1508C4 EP3C16F484C8N EP4SGF45I3
    Text: Revision: 1.3.0 PROCESS CHANGE NOTIFICATION P C N1 2 0 5 ADDITIONAL ASSEMBLY SOURCE ASE AND TRANSITION TO CENTER PIN GATE MOLD FOR FBGA PACKAGES Change Description This is an update to PCN1205; please see the revision history table for information specific to this


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    PCN1205; Reco0HF35I4 EP4SGX230HF35I4N EP4SGXHF35I3* EP4SGXKH40I3* EP4SGXKH40I3N* EP4SH40C2N* EP4SGF45I3* EP4SGX290NF45C2 PCN1205 EP3C120F780I7N EP4CE30F29I8LN EP4CGX50CF23C8 EP2SGX125GF1508C4 EP3C16F484C8N EP4SGF45I3 PDF

    pin information ep3c10

    Abstract: EP3C40F484 EP3c55 EP3C16F484 EP3C16 EP3C40Q240 EP3C40 U256 100 PIN PQFP ALTERA DIMENSION PIN INFORMATION FOR EP3C55
    Text: Cyclone Series Device Thermal Resistance July 2007, version 2.2 Revision History Data Sheet The following table shows the revision history for this data sheet. Date Document Version Changes Made July 2007 2.2 Updated values for EP3C25 E144 device in Table 2.


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    EP3C25 EP3C10 pin information ep3c10 EP3C40F484 EP3c55 EP3C16F484 EP3C16 EP3C40Q240 EP3C40 U256 100 PIN PQFP ALTERA DIMENSION PIN INFORMATION FOR EP3C55 PDF

    EP2C5

    Abstract: F256 LVDS11P LVDS20P a5201
    Text: Pin Information for the Cyclone II EP2C5 Device Version 1.9 Note 1 , (2) Bank Number VREFB Group Pin Name / Function Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1


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    pin configuration 1K variable resistor

    Abstract: EPC1441 EPC16 EPCS128 EPCS16 EPCS64 EPC8QC100 EPC8QC100 Pinout fpga JTAG Programmer Schematics ic 11105 circuits diagraM
    Text: Configuration Handbook Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com Config-1.3 September 2007 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


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    EP2C20

    Abstract: DDR2 pin out EP2C15A F256 EP2C20A
    Text: Cyclone II EP2C15A, EP2C20 & EP2C20A Device Pin-Out PT-EP2C20-2.1 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are


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    EP2C15A, EP2C20 EP2C20A PT-EP2C20-2 x16/x18 EP2C15A EP2C20 DDR2 pin out F256 PDF

    EP4CE15

    Abstract: EP4CE22 EP2AGX190 interlaken EP4CGX150 EP4CGX30 EP3SE50 EP4CE30 HC210 EP1C12
    Text: Quartus II Software Version 10.0 SP1 Device Support RN-01057 Release Notes This document provides late-breaking information about device support in the 10.0 SP1 version of the Altera Quartus® II software. For information about disk space and system requirements, refer to the readme.txt file in your


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    RN-01057 EP4CE15 EP4CE22 EP2AGX190 interlaken EP4CGX150 EP4CGX30 EP3SE50 EP4CE30 HC210 EP1C12 PDF

    transistor bt 808

    Abstract: BT 808 600 ADC 808 motion encoder chip block diagram of Video graphic array EP2C20 bt 808 camera de surveillance EP2C35 H.264 encoder ethernet
    Text: Low-Cost Solutions for Video Compression Systems Brian Jentz Altera Corporation 101 Innovation Drive San Jose, CA 95054, USA 408 544-7709 bjentz@altera.com Overview Many device applications utilize video compression to reduce the amount of data necessary to produce a sequence of images.


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    EP2CF256

    Abstract: AT91CAP7 AT91CAP7E AT91CAP7S sam-ba altera cyclone 2 digital photo frame 115200-8-N-1 AT91CAP7A AT91CAP7A-STK
    Text: Getting Started with eCos on Atmel AT91CAP7 Features • eCos overview • Development tools overview • Compilation and execution procedures 1. Introduction This application note describes the method of developing eCos applications for the Atmel AT91CAP7 customizable microcontroller and running them on the Atmel


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    AT91CAP7 AT91CAP7 AT91CAP7A-STK EP2CF256 AT91CAP7E AT91CAP7S sam-ba altera cyclone 2 digital photo frame 115200-8-N-1 AT91CAP7A PDF

    EPCS16SI8N

    Abstract: EPCS128 EPCS64SI16N EPCS16 EPCS 16 soic EPCS4 EPCS64 h5800 pin information ep3c5 EPCS1SI8N CG-250
    Text: 14. Serial Configuration Devices EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128 Data Sheet C51014-3.1 Introduction The serial configuration devices provide the following features: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 Altera Corporation May 2008


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    EPCS16, EPCS64, EPCS128) C51014-3 128-Mbit 16-pin EPCS64 EPCS16SI8N EPCS128 EPCS64SI16N EPCS16 EPCS 16 soic EPCS4 h5800 pin information ep3c5 EPCS1SI8N CG-250 PDF

    EPCS64SI16N

    Abstract: h2a0000 EPCS4SI8N EPCS16 EP2C20 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90
    Text: 4. Serial Configuration Devices EPCS1, EPCS4, EPCS16, & EPCS64 Features C51014-1.6 Introduction The serial configuration devices provide the following features: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1 Functional Description Altera Corporation


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    EPCS16, EPCS64) C51014-1 64-Mbit 16-pin EPCS16 EPCS16SI16N EPCS64 EPCS64SI16N EPCS64SI16N h2a0000 EPCS4SI8N EPCS16 EP2C20 EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 PDF

    CII51012-1

    Abstract: EP2C20 EP2C35 EP2C50
    Text: 12. Embedded Multipliers in Cyclone II Devices CII51012-1.2 Introduction Use Cyclone II FPGAs alone or as digital signal processing DSP co-processors to improve price-to-performance ratios for DSP applications. You can implement high-performance yet low-cost DSP


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    CII51012-1 EP2C20 EP2C35 EP2C50 PDF

    ep2c50f484

    Abstract: EP2C20F256 EP2C8F256 EP2C35F672 EP2C8F256 package TSMC 90nm sram EP2C5 pin table EP2C5F256 EP2C20F484 Cyclone II EP2C35
    Text: 1. Introduction CII51001-3.1 Introduction Following the immensely successful first-generation Cyclone device family, Altera® Cyclone II FPGAs extend the low-cost FPGA density range to 68,416 logic elements LEs and provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are


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    CII51001-3 300-mm 90-nm ep2c50f484 EP2C20F256 EP2C8F256 EP2C35F672 EP2C8F256 package TSMC 90nm sram EP2C5 pin table EP2C5F256 EP2C20F484 Cyclone II EP2C35 PDF

    pin configuration of 7496 IC

    Abstract: TMS 3617 Transistor TT 2246 ttl to mini-lvds EP2C35F672 IC 4033 pin configuration EP2C20F256 CI 4017 combinational digital lock circuit projects EP2C8F256
    Text: Cyclone II Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CII5V1-3.2 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


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    EP2C20

    Abstract: EP2C15A F256 LVDS48
    Text: Pin Information for the Cyclone II EP2C15A, EP2C20 & EP2C20A Devices Version 1.8 Note 1 , (2) Bank Number VREFB Group Pin Name / Function B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0


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    EP2C15A, EP2C20 EP2C20A x16/x18 EP2C15A EP2C20 F256 LVDS48 PDF