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Flip Electronics EP1S25F1020C6N IC FPGA 706 I/O 1020FBGA
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DigiKey	EP1S25F1020C6N	Tray	3,501		5	1 - 10 $146.67 100 $146.67 1000 $146.67 10000 $146.67	Buy Now
Flip Electronics EP1S25F1020C6 FIELD PROGRAMMABLE GATE ARRAY, 2
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DigiKey	EP1S25F1020C6	Tray	223		5	1 - 10 $729.41 100 $729.41 1000 $729.41 10000 $729.41	Buy Now
Intel Corporation EP1S25F1020C6 IC FPGA 706 I/O 1020FBGA
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DigiKey	EP1S25F1020C6	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Intel Corporation EP1S25F1020C6N IC FPGA 706 I/O 1020FBGA
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DigiKey	EP1S25F1020C6N	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Intel Corporation EP1S25F1020C6NGA EP1S25F1020C6NGA
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Verical	EP1S25F1020C6NGA		63		1	1 $300 10 $300 100 $255 1000 $255 10000 $255	Buy Now
Arrow Electronics	EP1S25F1020C6NGA		63	99 Weeks	1	1 $300 10 $300 100 $255 1000 $255 10000 $255	Buy Now

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EP1S25F1020C6 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Type	PDF
EP1S25F1020C6		Altera	Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 706 I/O 1020FBGA		Original	PDF
EP1S25F1020C6		Altera	Stratix FPGA 25K FBGA-1020		Original	PDF
EP1S25F1020C6		Altera	Programmable Logic Device		Original	PDF
EP1S25F1020C6N		Altera	Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 706 I/O 1020FBGA		Original	PDF
EP1S25F1020C6N		Altera	Stratix FPGA 25K FBGA-1020		Original	PDF
EP1S25F1020C6NGA		Altera	Integrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array) - IC FPGA STRATIX 1020FBGA		Original	PDF

EP1S25F1020C6 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
ddr333 pc2700 memory Abstract: DDR266 DDR333 EP1C20F400 EP1C20F400C6 EP1S25F1020C6 EP1S25F780C6 EP2A15F672C7 PC2100 PC2700 Text: DDR SDRAM Controller MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 1.1.0 1.1.0 rev 1 February 2003 DDR SDRAM Controller MegaCore Function User Guide	Original	PDF
PCN0902 Abstract: HC220F780NAK HC220F672nan HC210F484NAC XZ-092 HC230F1020BN HC240F1020NBC HC230F1020AW EP2S60F1020C4N EP2SGXF1152AA Text: Revision: 1.1.0 PROCESS CHANGE NOTIFICATION PCN0902 ADDITIONAL ASSEMBLY SOURCE AND BILL OF MATERIAL CHANGE FOR ALTERA FLIP CHIP PRODUCTS Change Description This is an update to PCN0902; please see the revision history table for information specific to this	Original	PDF	PCN0902 PCN0902; PCN0902 HC220F780NAK HC220F672nan HC210F484NAC XZ-092 HC230F1020BN HC240F1020NBC HC230F1020AW EP2S60F1020C4N EP2SGXF1152AA
"Stratix IV" Package layout information Abstract: EP1S25F780C7 EP1S30F780C7 S-51005 Text: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and	Original	PDF	EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* "Stratix IV" Package layout information EP1S25F780C7 EP1S30F780C7 S-51005
EP1S25F780C7 Abstract: EP1S30F780C7 Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original	PDF	EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S25F780C7 EP1S30F780C7
EP1S40F780C5 Abstract: EP1S25F780C7 EP1S30F780C7 ep1s20f484c6 EP1S20F484C7 Text: Stratix December 2002, ver. 3.0 Introduction Preliminary Information Features. Data Sheet The StratixTM family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements LEs and up to 10 Mbits of RAM. Stratix devices offer up to 28 digital signal	Original	PDF	420-MHz EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S40F780C5 EP1S25F780C7 EP1S30F780C7 ep1s20f484c6 EP1S20F484C7
IP-CSIX-L1 Abstract: EP1S10F780C5 EP1S10F780C6 EP1S25F1020C6 EP20K400EFC672-1X Text: Common Switch Interface CSIX-L1 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Core Version: 1.0.0 Document Version: 1.0.0 rev1 Document Date: November 2002 Copyright Common Switch Interface (CSIX-L1) MegaCore Function User Guide	Original	PDF
EP1S20F780C6 Abstract: EP1S25F780C7 EP1S30F780C7 EP1S20F484C7 3104 303 Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original	PDF	EP1S20B672C6 EP1S20 EP1S20B672C7 EP1S20F484C5 EP1S20F484C6 EP1S20F484C7 EP1S20F672C6 EP1S20F672C7 EP1S20F780C6 EP1S25F780C7 EP1S30F780C7 3104 303
EP1S25F780C7 Abstract: EP1S30F780C7 Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power	Original	PDF	EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S25F780C7 EP1S30F780C7
M512K Abstract: EP1S25F780C7 EP1S30F780C7 Text: Stratix February 2002, ver. 1.0 Introduction Preliminary Information Features. Data Sheet The Stratix family of programmable logic devices PLDs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices	Original	PDF	420-MHz EP1S60 EP1S80 EP1S120F1923C6 EP1S120 EP1S120F1923C7 M512K EP1S25F780C7 EP1S30F780C7