EP 1810 PROGRAM Search Results

EP 1810 PROGRAM Result Highlights (3)

Part	Manufacturer	Description
PAL16R8-4JC-UNPROGRAMMED	Rochester Electronics LLC	PAL16R8-4JC-UNPROGRAMMED
EP1810LC-35	Rochester Electronics LLC	EP1810 - Classic Family EPLD, Logic, 900 Gates, 48 Macrocells, 35ns, Commercial
EP1810GC-35	Rochester Electronics LLC	EP1810 - Classic Family EPLD, Logic, 900 Gates, 48 Macrocells, 35ns, Commercial

EP 1810 PROGRAM Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
max 7128S programmer Abstract: 7128E 10K30 EPF81188AGC232-3 ep600i altera 5032 PLSKT 10K20 epm9320 7160E Text: Ordering Information June 1996, ver. 8 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate	Original	304-pin PL-SKT/Q100 PL-SKT/Q160 PL-SKT/Q208 PL-SKT/Q240 PL-SKT/Q304 100-pin 208-pin 240-pin max 7128S programmer 7128E 10K30 EPF81188AGC232-3 ep600i altera 5032 PLSKT 10K20 epm9320 7160E	PDF
M5962 Abstract: ep 1810 program EP610 ORDERING 5032DM altera ep320 EPS448LC-25 EPM 5192 PLMD5032 J5192 EPS448 Text: Ordering EPLDs Figure 1 show s how an EPLD part num ber is constructed. For inform ation on specific package, grade, and speed com binations, refer to individual EPLD data sheets or the Product Selection Guide in this data book, or telephone the Altera M arketing D epartm ent at 408 984-2800.	OCR Scan	IL-STD-883-com Classi10/1810T EPM5016 PLMJ1810 PLEG1810 PLED5016 PLEJ5016 PLES5016 PLED5032 PLMD5032 M5962 ep 1810 program EP610 ORDERING 5032DM altera ep320 EPS448LC-25 EPM 5192 PLMD5032 J5192 EPS448	PDF
motorola HEP cross reference Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64 Text: BR1513/D Rev. 2, Apr-2001 ECLinPS Plus Device Data ECLinPS Plus Device Data Advanced ECL in Picoseconds BR1513/D Rev. 2, Apr–2001  SCILLC, 2001 Previous Edition  2000 “All Rights Reserved” ECLinPS, ECLinPS Lite, and ECLinPS Plus are trademarks of Semiconductor Components Industries, LLC.	Original	BR1513/D Apr-2001 r14525 DLD601 motorola HEP cross reference EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64	PDF
marking 7850 Abstract: No abstract text available Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D marking 7850	PDF
Untitled Abstract: No abstract text available Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D	PDF
TQFP 100 socket Abstract: No abstract text available Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10EP196/D TQFP 100 socket	PDF
MC100EP195 Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2	PDF
ic 4440 circuit diagram Abstract: MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D ic 4440 circuit diagram MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2	PDF
MC100EP196 Abstract: MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2 Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10EP196/D MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FA MC10EP196FAR2	PDF
MC10EP196FA Abstract: 10000 series of ECL gates ic 4440 circuit diagram MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FAR2 Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D MC10EP196FA 10000 series of ECL gates ic 4440 circuit diagram MC100EP196 MC100EP196FA MC100EP196FAR2 MC10EP196 MC10EP196FAR2	PDF
Untitled Abstract: No abstract text available Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10EP195/D	PDF
9560a Abstract: ALTERA MAX 3000 altera epc 610 10K30 altera ep 3128A 10K100E 20K300E altera 7096 ALTERA APU Text: Ordering Information July 2002, ver. 13 Altera Devices Figures 1 and 2 explain the ordering codes for Altera® devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. For information on specific package, speed grade,	Original	20K100, 9560a ALTERA MAX 3000 altera epc 610 10K30 altera ep 3128A 10K100E 20K300E altera 7096 ALTERA APU	PDF
ALTERA MAX 3000 Abstract: EPCS 16 soic Altera Programming Hardware 7128s 9560A Text: Ordering Information February 2003, ver. 14 Altera Devices Figures 1 and Figures 2 explain the ordering codes for Altera® devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. For information on specific package,	Original		PDF
Untitled Abstract: No abstract text available Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the	Original	MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D	PDF

EPCS 16 soic Abstract: ALTERA EP EPM3128ATC100-7 ep 1810 program altera marking 10K130E PL-APU 10K30 ADD-FLOATPC 20K30E Text: Ordering Information April 2003, ver. 15 Altera Devices Figures 1 and 2 explain the ordering codes for Altera® devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. For information on specific package, speed grade,	Original		PDF
208 pin rqfp drawing Abstract: 240 pin rqfp drawing ALTERA flex 81188 altera 5032 8636a EPF81188AGC232-3 100 PIN "PGA" ALTERA DIMENSION 5130a PL-SKT/Q160 Altera EPC Text: y /^ \ [^ V a \ Ordering Information M a rc h 19 95, ver. 7 Altera DBViC6S Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate	OCR Scan	208-pin 240-pin 304-pin PL-SKT/Q100 PL-SKT/Q160 PL-SKT/Q208 PL-SKT/Q240 PL-SKT/Q304 100-pin 208 pin rqfp drawing 240 pin rqfp drawing ALTERA flex 81188 altera 5032 8636a EPF81188AGC232-3 100 PIN "PGA" ALTERA DIMENSION 5130a Altera EPC	PDF
K 7256 M Abstract: max 7128S programmer PL-SKT/Q160 Text: Ordering Information June 1996, ver. 8 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have m ultiple pin counts for the same package include the pin count in their ordering codes. Som e codes use relative numbers e.g., -I, -2 to designate	OCR Scan	100-pin 160-pin 208-pin 240-pin 304-pin PL-SKT/Q100 PL-SKT/Q160 PL-SKT/Q208 PL-SKT/Q240 PL-SKT/Q304 K 7256 M max 7128S programmer	PDF
Altera flex 8k PCi Abstract: 10K50 10K30A altera epc 610 ALTERA MAX 5000 programming plcc 20pin socket EPM7032L 9560a flex 10k20 7160S Text: Ordering Information January 1998, ver. 9 Altera Devices Figure 1 explains the ordering codes for Altera devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to designate	Original	5000n 304-pin PL-SKT/Q100 PL-SKT/Q160 PL-SKT/Q208 PL-SKT/Q240 PL-SKT/Q304 100-pin 208-pin 240-pin Altera flex 8k PCi 10K50 10K30A altera epc 610 ALTERA MAX 5000 programming plcc 20pin socket EPM7032L 9560a flex 10k20 7160S	PDF
7032AE Abstract: 9560a Altera 7032 3128A 7256E 10K100A 7032B programmer EPLD 10K50 PL-ASAP Text: Ordering Information March 2001, ver. 10 Altera Devices Altera Corporation A-GN-ORD-10 Figure 1 explains the ordering codes for Altera® devices. Devices that have multiple pin counts for the same package include the pin count in their ordering codes. Some codes use relative numbers e.g., -1, -2 to	Original	-GN-ORD-10 7032B 7032AE 9560a Altera 7032 3128A 7256E 10K100A programmer EPLD 10K50 PL-ASAP	PDF
MC10EP01 Abstract: No abstract text available Text: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD	Original	MC10EP016, MC100EP016 MC10/100EP016 MC10E016 MC100EP016 AND8020 MC10EP01	PDF
Untitled Abstract: No abstract text available Text: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 MC10EP195/D	PDF
Untitled Abstract: No abstract text available Text: 3.3V 3.2Gbps SONET/SDH LASER DRIVER FEATURES • ■ ■ ■ ■ ■ ■ SY88912L DESCRIPTION Up to 3.2Gbps operation Modulation current to 60mA Rise/Fall times <70PS Single 3.3V power supply Programmable laser modulation current Operating temperature range of –40°C to 85°C	Original	16-pin SY88912L SY88912L for16-Pin	PDF
MC100EP195 Abstract: MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 marking EE Text: MC10EP195, MC100EP195 3.3V ECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and	Original	MC10EP195, MC100EP195 MC10/100EP195 EP195 MC10EP195/D MC100EP195 MC100EP195FA MC100EP195FAR2 MC10EP195 MC10EP195FA MC10EP195FAR2 marking EE	PDF
Untitled Abstract: No abstract text available Text: 3.3V 3.2Gbps SONET/SDH LASER DRIVER FEATURES • ■ ■ ■ ■ ■ ■ SY88912L FINAL DESCRIPTION Up to 3.2Gbps operation Modulation current to 60mA Rise/Fall times <70PS Single 3.3V power supply Programmable laser modulation current Operating temperature range of –40°C to 85°C	Original	SY88912L 16-pin SY88912L	PDF

EP 1810 PROGRAM Search Results

EP 1810 PROGRAM Result Highlights (3)

EP 1810 PROGRAM Datasheets Context Search

max 7128S programmer

M5962

motorola HEP cross reference

marking 7850

Untitled

TQFP 100 socket

MC100EP195

ic 4440 circuit diagram

MC100EP196

MC10EP196FA

Untitled

9560a

ALTERA MAX 3000

Untitled

EPCS 16 soic

208 pin rqfp drawing

K 7256 M

Altera flex 8k PCi

7032AE

MC10EP01

Untitled

Untitled

MC100EP195

Untitled