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    ELPIDA DLL CIRCUIT Search Results

    ELPIDA DLL CIRCUIT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TLP2701 Toshiba Electronic Devices & Storage Corporation Photocoupler (photo-IC output), 5000 Vrms, 4pin SO6L Visit Toshiba Electronic Devices & Storage Corporation
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    TCKE800NA Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Auto-retry, WSON10B Visit Toshiba Electronic Devices & Storage Corporation
    TCKE800NL Toshiba Electronic Devices & Storage Corporation eFuse IC (electronic Fuse), 4.4 to 18 V, 5.0 A, Latch, WSON10B Visit Toshiba Electronic Devices & Storage Corporation

    ELPIDA DLL CIRCUIT Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    C10A

    Abstract: No abstract text available
    Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442- C10A, 45D128842- C10A, 45D128164- C10A 128 M-bit Synchronous DRAM with Double Data Rate 4-bank, SSTL_2 Description The µPD45D128442-C10A, 45D128842-C10A, 45D128164-C10A are high-speed 134,217,728 bits synchronous


    Original     		PDF PD45D128442- 45D128842- 45D128164- PD45D128442-C10A, 45D128842-C10A, 45D128164-C10A 608x4x4, 304x8x4, 152x16x4 66-pin C10A

    elpida DLL circuit

    Abstract: elpida ELPIDA ddr2 chip EDE2108AASE
    Text: PRELIMINARY DATA SHEET 2G bits DDR2 SDRAM EDE2104AASE 512M words x 4 bits EDE2108AASE (256M words × 8 bits) Description Features The EDE2104AASE is a 2G bits DDR2 SDRAM organized as 67,108,864 words × 4 bits × 8 banks. The EDE2108AASE is a 2G bits DDR2 SDRAM


    Original     		PDF EDE2104AASE EDE2108AASE EDE2104AASE EDE2108AASE 68-ball M01E0107 E0757E10 elpida DLL circuit elpida ELPIDA ddr2 chip

    elpida DLL circuit

    Abstract: elpida EDE2108
    Text: PRELIMINARY DATA SHEET 2G bits DDR2 SDRAM EDE2104AASE 512M words x 4 bits EDE2108AASE (256M words × 8 bits) Description Features The EDE2104AASE is a 2G bits DDR2 SDRAM organized as 67,108,864 words × 4 bits × 8 banks. The EDE2108AASE is a 2G bits DDR2 SDRAM


    Original     		PDF EDE2104AASE EDE2108AASE EDE2104AASE EDE2108AASE 68-ball M01E0107 E0757E11 elpida DLL circuit elpida EDE2108

    uPD45D128164G5-C75-9LG

    Abstract: uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG
    Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate 4-bank, SSTL_2 Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.


    Original     		PDF PD45D128442, 45D128842, 45D128164 45D128164 608x4x4, 304x8x4, 152x16x4 66-pin uPD45D128164G5-C75-9LG uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2516AKTA 16M words x 16 bits Description Pin Configurations The EDD2516AK is a 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at


    Original     		PDF EDD2516AKTA EDD2516AK 66-pin M01E0107 E0303E20

    DDR400

    Abstract: BT122
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AMTA-5 is a 256M bits


    Original     		PDF EDD2508AMTA-5 DDR400) EDD2516AMTA-5 EDD2508AMTA-5 EDD2516AMTA-5 M01E0107 E0406E10 DDR400 BT122

    AX12

    Abstract: DDR400 DDR400B
    Text: DATA SHEET 256M bits DDR SDRAM EDD2508ARTA-5B 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508ARTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at


    Original     		PDF EDD2508ARTA-5B DDR400) EDD2508ARTA 66pin M01E0107 E0772E10 AX12 DDR400 DDR400B

    EDD2516AMTA-6B-E

    Abstract: auto-10
    Text: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for


    Original     		PDF EDD2516AMTA-6B-E EDD2516AMTA 66pin M01E0107 E0749E10 EDD2516AMTA-6B-E auto-10

    AX12

    Abstract: DDR400 DDR400B BT122
    Text: DATA SHEET 256M bits DDR SDRAM EDD2508ARTA-5B 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508ARTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at


    Original     		PDF EDD2508ARTA-5B DDR400) EDD2508ARTA 66pin 66-pin M01E0107 E0772E10 AX12 DDR400 DDR400B BT122

    BT122

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits DDR SDRAM EDD2516ARTA-6B 16M words x 16 bits Specifications Pin Configurations • Density: 256M bits • Organization  4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) • Power supply: VDD, VDDQ = 2.5V ± 0.2V


    Original     		PDF EDD2516ARTA-6B 66-pin 333Mbps cycles/64ms M01E0107 E0848E10 BT122

    AX12

    Abstract: DDR400 DDR400B BT122
    Text: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at


    Original     		PDF EDD2508AMTA-5B-E DDR400) EDD2508AMTA 66pin 66-pin M01E0107 E0750E10 AX12 DDR400 DDR400B BT122

    AX12

    Abstract: DDR400 DDR400B BT122
    Text: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at


    Original     		PDF EDD2508AMTA-5B-E DDR400) EDD2508AMTA 66pin M01E0107 E0750E10 AX12 DDR400 DDR400B BT122

    EDD2516AMTA-6B-E

    Abstract: BT122
    Text: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for


    Original     		PDF EDD2516AMTA-6B-E EDD2516AMTA 66pin 66-pin M01E0107 E0749E10 EDD2516AMTA-6B-E BT122

    BT122

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Description Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR


    Original     		PDF EDD2508AMTA EDD2516AMTA EDD2508AM EDD2516AM M01E0107 E0405E10 BT122

    BT122

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR


    Original     		PDF EDD2508AMTA EDD2516AMTA EDD2508AM EDD2516AM M01E0107 E0405E10 BT122

    DDR400

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Description Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8


    Original     		PDF EDD2508AMTA-5 DDR400) EDD2516AMTA-5 EDD2508AMTA-5 EDD2516AMTA-5 M01E0107 E0406E10 DDR400

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data


    Original     		PDF EDD1232AABH-5 DDR400) EDD1232AABH 144-ball 400Mbps M01E0107 E0532E40

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 128M bits DDR SDRAM EDD1232AABH-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data


    Original     		PDF EDD1232AABH-5 DDR400) EDD1232AA 144-ball 400Mbps M01E0107 E0532E30

    DDR400

    Abstract: No abstract text available
    Text: DATA SHEET 256M bits DDR SDRAM EDD2516AKTA-5-E 16M words x 16 bits, DDR400 Description Pin Configurations The EDD2516AKTA-5 is a 256M bits DDR SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross


    Original     		PDF EDD2516AKTA-5-E DDR400) EDD2516AKTA-5 66-pin 400Mbpsribed M01E0107 E0638E20 DDR400

    DDR400

    Abstract: EDD1232AAFA-5C-E
    Text: PRELIMINARY DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data


    Original     		PDF EDD1232AAFA-5 DDR400) EDD1232AA 100-pin 400Mbps M01E0107 E0401E30 DDR400 EDD1232AAFA-5C-E

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET 128M bits DDR SDRAM EDD1232AAFA-5 4M words x 32 bits, DDR400 Description Features The EDD1232AAFA is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data


    Original     		PDF EDD1232AAFA-5 DDR400) EDD1232AAFA 100-pin 400Mbps M01E0107 E0401E40

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AKTA-5-E 32M words x 8 bits, DDR400 Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 8M words × 8 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant)


    Original     		PDF EDD2508AKTA-5-E DDR400) 66-pin 400Mbps cycles/64ms M01E0107 E0609E30

    EDD1232ABBH

    Abstract: EDD1232ABBH-5C-E
    Text: DATA SHEET 128M bits DDR SDRAM EDD1232ABBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization ⎯ 1M words × 32 bits × 4 banks • Package: 144-ball FBGA ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.125V


    Original     		PDF EDD1232ABBH 144-ball 400Mbps M01E0107 E0874E40 EDD1232ABBH EDD1232ABBH-5C-E

    DDR400B

    Abstract: No abstract text available
    Text: DATA SHEET 128M bits DDR SDRAM EDD1232ACBH 4M words x 32 bits Specifications Features • Density: 128M bits • Organization  1M words × 32 bits × 4 banks • Package: 144-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 2.5V −0.125V/+0.2V


    Original     		PDF EDD1232ACBH 144-ball 400Mbps M01E0706 E1202E20 DDR400B