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Abstract: No abstract text available
Text: AVG Semiconductors DDi Technical Data 113 Dual JK Negative Edge-Triggered Flip-Flops with PRESET DV74LS113A DV74ALS113A N Suffix Plastic DIP AVG-001 Case This device contains individual J, K, set, and clock inputs. When the clock goes HIGH, the inputs are enabled and data
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DV74LS113A
DV74ALS113A
AVG-001
AVG-002
DV74LS113A,
1-800-AVG-SEMI
LS113A
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LS113
Abstract: No abstract text available
Text: DDT A VG S em iconductors Technical Data Dual JK Negative Edge-Triggered Flip-Flops with PRESET D V74LS113A D V 7 4 A L S 1 13A N Suffix P lastic DIP AVG-001 Case This device contains individual J, K, set, and clock inputs. When the clock goes HIGH, the inputs are enabled and data
|
OCR Scan
|
PDF
|
DV74LS113A
DV74ALS113A
AVG-001
AVG-002
DV74LS113A,
1-800-AVG-SEMI
LS113A
ALS113A
LS113
|