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    DUAL FLIP FLOP TRISTATE Search Results

    DUAL FLIP FLOP TRISTATE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74ACT11175DW Rochester Electronics LLC D Flip-Flop, Visit Rochester Electronics LLC Buy
    SN54LS107J Rochester Electronics LLC J-K Flip-Flop Visit Rochester Electronics LLC Buy
    FO-DUALSTLC00-001 Amphenol Cables on Demand Amphenol FO-DUALSTLC00-001 ST-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x ST Male to 2 x LC Male 1m Datasheet
    FO-DUALSTLC00-004 Amphenol Cables on Demand Amphenol FO-DUALSTLC00-004 ST-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x ST Male to 2 x LC Male 4m Datasheet
    FO-LSDUALSCSM-003 Amphenol Cables on Demand Amphenol FO-LSDUALSCSM-003 SC-SC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFN-LS Low Smoke) - 2 x SC Male to 2 x SC Male 3m Datasheet

    DUAL FLIP FLOP TRISTATE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: SCAN18374T SCAN18374T D Flip-Flop with TRI-STATE Outputs Literature Number: SNLS037 SCAN18374T D Flip-Flop with TRI-STATE Outputs General Description Features The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual


    Original     		PDF SCAN18374T SCAN18374T SNLS037

    74sc

    Abstract: 74F74
    Text: 54F74,74F74 54F74 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop Literature Number: SNOS214A 54F 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Military 74F74PC Package Number Features Y Guaranteed 4000V minimum ESD protection


    Original     		PDF 54F74 74F74 74F74 SNOS214A 74sc

    54F74DM

    Abstract: 74F74 pmi op07 54F74FM 54F74LM 74F74PC 74F74SC 74F74SJ J14A M14A
    Text: 54F 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q Q outputs Information at the input is transferred to the outputs on the positive edge of


    Original     		PDF 74F74 74F74PC 20-3A 54F74DM 74F74 pmi op07 54F74FM 54F74LM 74F74PC 74F74SC 74F74SJ J14A M14A

    74F74DC

    Abstract: M074 74f74d 74F74
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 11/18/96 Last Update Date: 06/19/97 Last Major Revision Date: 04/17/97 CN74F74-X REV 1A0 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary


    Original     		PDF CN74F74-X M0001326 74F74DC M074 74f74d 74F74

    54F74DMQB

    Abstract: MN54F74-X 54F74 54F74FMQB 54F74LMQB
    Text: MILITARY DATA SHEET Original Creation Date: 03/13/96 Last Update Date: 07/30/96 Last Major Revision Date: 03/13/96 MN54F74-X REV 1A0 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary


    Original     		PDF MN54F74-X -55/125C, 54F74DMQB 54F74 54F74FMQB 54F74LMQB

    74F109

    Abstract: 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A
    Text: 54F 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed completely independent transition clocked JK flip-flops The clocking operation is independent of rise and fall times of the clock waveform The JK design allows operation as a D flip-flop refer to ’F74


    Original     		PDF 74F109 74F109PC 16-Lead 20-3A 74F109 9471 54F109DM 54F109FM 54F109LM 74F109PC 74F109SC 74F109SJ F109 J16A

    54F74

    Abstract: 54F74DC
    Text: MICROCIRCUIT DATA SHEET Original Creation Date: 06/25/97 Last Update Date: 07/08/97 Last Major Revision Date: 06/25/97 CN54F74-X REV 0A0 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary


    Original     		PDF CN54F74-X M0001736 CN74F CN54F 54F74 54F74DC

    74LCX112

    Abstract: 74LCX112M 74LCX112MX 74LCX112SJ M16A
    Text: 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs Q, Q outputs. These devices are edge sensitive and change state


    Original     		PDF 74LCX112 74LCX112 ds012424 74LCX112M 74LCX112MX 74LCX112SJ M16A

    74LCX109MTC

    Abstract: "J-K Flip flops" 74LCX109 74LCX109SJ 74LCX109SJX M16D Fairchild Semiconductor technology
    Text: November 1996 74LCX109 Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX109 are dual J-K flip-flops. Each flip-flop has independent J, K , PRESET, CLEAR, and CLOCK inputs and Q, Q outputs. These devices are edge sensitive and change


    Original     		PDF 74LCX109 74LCX109 74LCX109MTC "J-K Flip flops" 74LCX109SJ 74LCX109SJX M16D Fairchild Semiconductor technology

    M16D

    Abstract: MTC16 74LCX109 74LCX109M 74LCX109MTC 74LCX109MTCX 74LCX109MX 74LCX109SJ 74LCX109SJX M16A
    Text: November 1996 74LCX109 Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX109 are dual J-K flip-flops Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs and Q Q outputs These devices are edge sensitive and change


    Original     		PDF 74LCX109 74LCX109 M16D MTC16 74LCX109M 74LCX109MTC 74LCX109MTCX 74LCX109MX 74LCX109SJ 74LCX109SJX M16A

    "J-K Flip flops"

    Abstract: 74LCX112MTC 74LCX112 74LCX112M 74LCX112MTCX 74LCX112MX 74LCX112SJ 74LCX112SJX C1996 M16D
    Text: December 1996 74LCX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear with 5V Tolerant Inputs General Description Features The 74LCX112 are dual J-K flip-flops Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs Q Q outputs These devices are edge sensitive and change state


    Original     		PDF 74LCX112 74LCX112 "J-K Flip flops" 74LCX112MTC 74LCX112M 74LCX112MTCX 74LCX112MX 74LCX112SJ 74LCX112SJX C1996 M16D

    SCAN18374T

    Abstract: No abstract text available
    Text: SCAN18374T D Flip-Flop with TRI-STATE Outputs General Description Features The SCAN18374T is a high speed, low-power D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals. This device is compliant with IEEE 1149.1 Standard


    Original     		PDF SCAN18374T SCAN18374T da959

    E 94733

    Abstract: E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D
    Text: 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The ’F113 offers individual J K Set and Clock inputs When the clock goes HIGH the inputs are enabled and data may be entered The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop will


    Original     		PDF 74F113 74F113PC 74F113SC 14-Lead E 94733 E 94733 3 74F113 74F113PC 74F113SC 74F113SJ C1995 F113 M14A M14D

    tms 374

    Abstract: C1995 SCAN182374A SCAN182374AFMQB SCAN182374ASSC SCAN182374ASSCX 11545 F-11545 B-500 diode
    Text: SCAN182374A Serially Controlled Access Network D Flip-Flop with 25X Series Resistor Outputs General Description Features The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable control signals This device is compliant with IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture with


    Original     		PDF SCAN182374A SCAN182374A 20-3A tms 374 C1995 SCAN182374AFMQB SCAN182374ASSC SCAN182374ASSCX 11545 F-11545 B-500 diode

    Untitled

    Abstract: No abstract text available
    Text: £3 National Æm Semiconductor 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of


    OCR Scan     		PDF 54F/74F74

    Untitled

    Abstract: No abstract text available
    Text: <ß National Semiconductor 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q, Ü outputs. Information at the input is transferred to the outputs on the positive edge of


    OCR Scan     		PDF 54F/74F74 bSD1152

    Untitled

    Abstract: No abstract text available
    Text: National Semiconductor 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q, Ü outputs. Information at the input is transferred to the outputs on the positive edge of


    OCR Scan     		PDF 54F/74F74

    Untitled

    Abstract: No abstract text available
    Text: 182374A Na ti o n al Semiconductor SCAN 182374A D Flip-Flop with 25fl Series Resistor Outputs General Description Features The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual 9-bit bytes with byte-oriented clock and output enable con­


    OCR Scan     		PDF 82374A SCAN182374A MIL-STD-683B,

    m074

    Abstract: 54F74fm
    Text: & Na t i o n a I Semiconductor MILITARY DATA SHEET Original Creation Date: Last Update Date: Last Major Revision Date: MN54F74-X REV 1A0 03/13/96 07/30/96 03/13/96 DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary


    OCR Scan     		PDF MN54F74-X m074 54F74fm

    gu43

    Abstract: tms 374 BU 2735 AS SCAN182374A SCAN182374ASSC
    Text: 182374A N a t i o n a l S e m i c o n d u c t o r SCAN182374A Serially Controlled Access Network D Flip-Flop with 25ft Series Resistor Outputs General Description Features The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual


    OCR Scan     		PDF SCAN182374A SCAN182374A bSD1155 gu43 tms 374 BU 2735 AS SCAN182374ASSC

    Untitled

    Abstract: No abstract text available
    Text: 182374A N a t i o n a l S e m i c o n d u c t o r SCAN 182374A Serially Controlled Access Network D Flip-Flop with 25S1 Series Resistor Outputs General Description Features The SCAN182374A is a high performance BiCMOS D-type flip-flop featuring separate D-type inputs organized into dual


    OCR Scan     		PDF 82374A SCAN182374A

    Untitled

    Abstract: No abstract text available
    Text: Semiconductor December 1994 54F/74F74 Dual D-Type Positive Edge-Triggered Flip-Flop General Description The ’F74 is a dual D-type flip-fjop with Direct Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of


    OCR Scan     		PDF 54F/74F74 74F74PC 20-3A

    74F109

    Abstract: No abstract text available
    Text: National Semiconductor 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely indepen­ dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform.


    OCR Scan     		PDF 54F/74F109 74F109

    Untitled

    Abstract: No abstract text available
    Text: • bSOliaS □□733TM 1S1 ■ National NS August 1992 Æ m Semiconductor " P 4 _ i - 0 1 - 0 $ 74FR74«74FR1074 Dual D-Type Flip-Flop General Description Features The 'FR74 and ’FR1074 are dual D-type flip-flops with true and complement (Q/Q outputs. On the 'FR74, data at the


    OCR Scan     		PDF T4FR74 74FR1074 733TM 74FR74 FR1074