DPLL Search Results

DPLL Result Highlights (6)

Part	Manufacturer	Description
8A34042B-000NLG8	Renesas Electronics Corporation	Multichannel DPLL / DCO - Four Channels
8A34042C-000NLG#	Renesas Electronics Corporation	Multichannel DPLL / DCO - Four Channels
8A34043E-000NBG	Renesas Electronics Corporation	Multichannel DPLL / DCO - Four Channels
8A34041B-000AJG	Renesas Electronics Corporation	Multichannel DPLL / DCO - Eight Channels
8A34041C-000AJG8	Renesas Electronics Corporation	Multichannel DPLL / DCO - Eight Channels
8A34042E-000NLG	Renesas Electronics Corporation	Multichannel DPLL / DCO - Four Channels

DPLL Price and Stock

Filter by Manufacturer


Renesas Electronics Corporation R5F10DPLLFB#H2G IC MCU 16BIT 512KB FLASH 100LQFP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	R5F10DPLLFB#H2G	Tray	720		1	1 $10.46 10 $9.446 100 $7.82038 1000 $6.80993 10000 $5.93122	Buy Now
Avnet Americas	R5F10DPLLFB#H2G	Tray		12 Weeks	720	1 - 10 - 100 - 1000 $6.3075 10000 $5.655	Buy Now
Mouser Electronics	R5F10DPLLFB#H2G					1 - 10 - 100 - 1000 $5.93 10000 $5.93	Get Quote
Renesas Electronics America	R5F10DPLLFB#H2G	Tray	720		1	1 $10.46 10 $9.446 100 $7.82038 1000 $6.80993 10000 $5.93122	Buy Now
STMicroelectronics EVL90WADP-LLCSR EVAL BOARD PORTABLE PWR SUPPLY
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	EVL90WADP-LLCSR	Bulk				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Kyocera AVX Components CKR22CH150DP-LL CAP CER 15PF 200V C0H 2-DIP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CKR22CH150DP-LL	Bulk			200	1 - 10 - 100 - 1000 $27.24865 10000 $27.24865	Buy Now
Renesas Electronics Corporation R5F10DPLLFB#X6G 16BIT MCU RL78/D1A 512K LFQFP100
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	R5F10DPLLFB#X6G	Reel			1,000	1 - 10 - 100 - 1000 $5.93122 10000 $5.93122	Buy Now
Avnet Americas	R5F10DPLLFB#X6G	Reel		12 Weeks	1,000	1 - 10 - 100 - 1000 $6.3075 10000 $5.655	Buy Now
Mouser Electronics	R5F10DPLLFB#X6G					1 - 10 - 100 - 1000 $5.84 10000 $5.84	Get Quote
Kyocera AVX Components CKR22CG270DP-LL CAP CER 27PF 200V NP0 2-DIP
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CKR22CG270DP-LL	Bulk			200	1 - 10 - 100 - 1000 $102.9882 10000 $102.9882	Buy Now
Newark	CKR22CG270DP-LL	Bulk			200	1 - 10 - 100 $85.11 1000 $85.11 10000 $85.11	Buy Now

Find more DPLL price and stock on Findchips.com

DPLL Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
DS31408GN Abstract: No abstract text available Text: ABRIDGED DATA SHEET 19-5659; Rev 2; 2/11 DS31408 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock General Description The DS31408 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its eight input clocks	Original	PDF	DS31408 14-Output, DS31408 750MHz. 24MHz, 48MHz, 10MHz, 20MHz, 44MHz, 88MHz DS31408GN
CVPD-024 Abstract: verilog DPLL XAPP854 AD5320 XAPP514 ROCKETIO X854 x8540 VERILOG Digitally Controlled Oscillator verilog code for phase detector Text: Application Note: Virtex-4 FPGAs R XAPP854 v1.0 October 10, 2006 Digital Phase-Locked Loop (DPLL) Reference Design Author: Justin Gaither Summary Many applications require a clock signal to be synchronous, phase-locked, or derived from another signal, such as a data signal or another clock. This type of clock circuit is important in	Original	PDF	XAPP854 UG024, UG029, XAPP514, CVPD-024 verilog DPLL XAPP854 AD5320 XAPP514 ROCKETIO X854 x8540 VERILOG Digitally Controlled Oscillator verilog code for phase detector
GR-1244-CORE Abstract: ZL50015 ZL50015GAC ZL50015QCC ZL50015QCC1 Text: ZL50015 Enhanced 1 K Digital Switch with Stratum 4E DPLL Data Sheet Features • January 2006 1024 channel x 1024 channel non-blocking digital Time Division Multiplex TDM switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and	Original	PDF	ZL50015 ZL50015GAC ZL50015QCC ZL50015QCC1 ZL50015GAG2 GR-1244-CORE ZL50015 ZL50015GAC ZL50015QCC ZL50015QCC1
Untitled Abstract: No abstract text available Text: ZL30153 Synchronous Ethernet Network Synchronization DPLL Short Form Data Sheet February 2012 Features • • Ordering Information ZL30153GGG 100 Pin LBGA ZL30153GGG2 100 Pin LBGA* Supports requirements of ITU-T G.8262 for Synchronous Ethernet Equipment Slave Clocks	Original	PDF	ZL30153 ZL30153GGG ZL30153GGG2 -40oC GR-1244 GR-253,
ZL50011QCG1 Abstract: GR-1244-CORE MS-026 ZL50011 Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features • March 2006 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation Ordering Information 160 Pin LQFP Trays 144 Ball LBGA Trays 160 Pin LQFP* Trays, Bake & Drypack	Original	PDF	ZL50011 ZL50011/QCC ZL50011/GDC ZL50011QCG1 ZL50011GDG2 GR-1244-CORE ZL50011QCG1 MS-026 ZL50011
ZL50010 Abstract: TFR1M GR-1244-CORE MS-026 Text: ZL50010 Flexible 512-ch DX with Enhanced DPLL Data Sheet Features VDD ZL50010/QCC ZL50010/GDC • • • • • • • • RESET Data Memory P/S Converter Output HiZ Control Connection Memory Microprocessor Interface and DPLL OSC Output Timing STo0-15 STOHZ0-15	Original	PDF	ZL50010 512-ch STi0-15 ZL50010/QCC ZL50010/GDC IEEE-1149 ZL50010 TFR1M GR-1244-CORE MS-026
Untitled Abstract: No abstract text available Text: ZL30161 Network Synchronization Clock Translator Short Form Data Sheet May 2013 Features • Ordering Information ZL30161GDG2 144 Pin LBGA Trays Fully compliant SEC G.813 and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL) Pb Free Tin/Silver/Copper	Original	PDF	ZL30161 ZL30161GDG2 -40oC
Untitled Abstract: No abstract text available Text: ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail	Original	PDF	ZL30112 ZL30112
Untitled Abstract: No abstract text available Text: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features September 2011 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps	Original	PDF	ZL50019 GR-1244-CORE ZL50019GAC ZL50019QCG1 ZL50019GAG2
Untitled Abstract: No abstract text available Text: Short Form Data Sheet April 2012 MAX24305, MAX24310 5- or 10-Output Any-Rate Timing ICs with Internal EEPROM General Description The MAX24305 and MAX24310 are flexible, highperformance timing and clock synthesizer ICs that include a DPLL and two independent APLLs. When	Original	PDF	MAX24305, MAX24310 10-Output MAX24305 MAX24310 750MHz
APP4391 Abstract: DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE Text: Maxim > App Notes > Communications Circuits T/E Carrier and Packetized Keywords: stratum 3, stratum 3E, stratum 4E, G.813, G.812, clock, clock sync, clock synchronization, timing card, timing IC, DPLL, master-slave, redundancy, telecom, SONET, SDH, clock sync, sonet, sdh, equipment	Original	PDF	DS3104: DS3105: DS3106: com/an4391 AN4391, APP4391, Appnote4391, APP4391 DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE
Untitled Abstract: No abstract text available Text: Port Synchronizer for IEEE 1588 and Synchronous Ethernet 82P33724 SHORT FORM DATA SHEET HIGHLIGHTS • • • • • • DPLL1 and DPLL2 can be used on line cards to manage the generation of synchronous port clocks and IEEE 1588 synchronization signals based on multiple system backplane references	Original	PDF	82P33724 1000BASE-T 1000BASE-X
GR-1244-CORE Abstract: ZL50019 ZL50019GAC ZL50019QCC Text: ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps	Original	PDF	ZL50019 GR-1244-CORE ZL50019 ZL50019GAC ZL50019QCC
GR-1244-CORE Abstract: MS-026 ZL50011 11CH marking Text: ZL50011 Flexible 512 Channel DX with on-chip DPLL Data Sheet Features July 2004 • 512 channel x 512 channel non-blocking switch at 2.048 Mbps, 4.096 Mbps or 8.192 Mbps operation • Rate conversion between the ST-BUS inputs and ST-BUS outputs • Integrated Digital Phase-Locked Loop DPLL	Original	PDF	ZL50011 GR-1244-CORE MS-026 ZL50011 11CH marking

GR-1244-CORE Abstract: GR-253-CORE ZL30106 ZL30106QDG "network interface cards" Text: ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • • • • • • • • October 2004 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH	Original	PDF	ZL30106 GR-1244-CORE GR-253-CORE ZL30106 ZL30106QDG "network interface cards"
GR-1244-CORE Abstract: GR-253-CORE ZL30102 ZL30105 Stratum 3 digital PLL Text: ZL30102 /5 REDUNDANT SYSTEM CLOCK SYNCHRONIZER DPLLs VOICE/DATA ZL30105 Simplified Block Diagram Enhanced Features for PDH and SDH Redundant Clock Interface Synchronization J'%;'%I:>IjhWjkc H[ZkdZWdj Ioij[c9beYaIodY^hed_p[h Reference Clock Inputs Redundant	Original	PDF	ZL30102 ZL30105 PP5877 GR-1244-CORE GR-253-CORE Stratum 3 digital PLL
ZL50018 Abstract: GR-1244-CORE ZL50018GAC ZL50018QCC MFU 78 Text: ZL50018 2 K Digital Switch with Enhanced Stratum 3 DPLL Data Sheet Features November 2006 • 2048 channel x 2048 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or	Original	PDF	ZL50018 GR-1244-CORE ZL50018GAC ZL50018QCC ZL50018QCG1 ZL50018GAG2 ZL50018 ZL50018GAC ZL50018QCC MFU 78
Untitled Abstract: No abstract text available Text: ZL50022 Enhanced 4 K Digital Switch with Stratum 4E DPLL Data Sheet Features 4096 channel x 4096 channel non-blocking digital Time Division Multiplex TDM switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps	Original	PDF	ZL50022 GR-1244-CORE ZL50022GAC 256-ball ZL50022QCC 256-lead
siemens sab 82532 Abstract: 82258 SA 82532 SAB 80286 csc 2323 sab80286 STT 3 SIEMENS 80286 microprocessor pin out diagram ESCC2 siemens sab 82525 Text: SIEM ENS Enhanced Serial Communication Controller ESCC2 SAB 82532 Preliminary Data 1.1 CMOS 1C General Features S erial Interface • Two independent full duplex serial channels - On chip clock generation or external clock source - On chip DPLL for clock recovery of each	OCR Scan	PDF	CRC-32 235b05 82532N-10. 00702fl2 siemens sab 82532 82258 SA 82532 SAB 80286 csc 2323 sab80286 STT 3 SIEMENS 80286 microprocessor pin out diagram ESCC2 siemens sab 82525
siemens sab 82538 Abstract: 3tb siemens T-0657 SiEMENS PM 350 98 SAB 80188 QD70 SIEMENS ESCC8 1fa MARKING processor hbt 00 04 g Q67100-H6441 Text: SIEM ENS Enhanced Serial Communication Controller ESCC8 SAB 82538 SAF 82538 Preliminary Data 1 CMOS 1C General Features Serial Interface • Eight independent full duplex serial channels - On chip clock generation or external clock source - On chip DPLL for clock recovery of each	OCR Scan	PDF	CRC-32 fl23Sb05 siemens sab 82538 3tb siemens T-0657 SiEMENS PM 350 98 SAB 80188 QD70 SIEMENS ESCC8 1fa MARKING processor hbt 00 04 g Q67100-H6441
Untitled Abstract: No abstract text available Text: r z 7 S C S -T H O M S O N « « L E M « ! _ T S 6 8 9 5 2 ^ 7# MODEM TRANSMIT/RECEIVE CLOCK GENERATOR • INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS ■ TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL	OCR Scan	PDF	TS68952 50-pins TS68930 TS68950/51/52
Untitled Abstract: No abstract text available Text: A . T h t da djpi a r t Ic th proporty oP Anphanol Corporation ind Ic dpllvorpoi or •fchr B xp r e s g c o n d itio n t h a t r t Is m i 'bo b e e ls c lo s B d ^ r v p r p o lv c v d o r u s e d Iki n H ^ a o r Iki p t r t , F o r n a .r u f i i E t u r r a r n l v b y o n y o iw g f w	OCR Scan	PDF	SSN001
TS68950 Abstract: TS68951 TS68952 V27bis digital clock diagram Text: C THOMSON SEMICONDUCTEURS TS68950 • TS68951 • TS68952 MODEM INTERFACE FOR SIGNAL PROCESSING Kit of 3 integrated circuits : MODEM Anafog Front End MAFE TS68950: Analog transmit interface TS68951: Analog receive interface TS68952: DPLL Tx/Rx clock generator	OCR Scan	PDF	TS68950 TS68951 TS68952 TS68950: TS68951: TS68952: 12-bit 240780F TS68952 TS68950 TS68951 V27bis digital clock diagram
MAP32 Abstract: No abstract text available Text: CL-CD2431 A dvanced M ulti-Protocol C om m unications Controller 1CIRRUS LOGIC Bit Index Numerics AbortTx 116-118 AdMd[1:0] 86 AFLO 86 A lti 93 AppdCmp 118 Append 150 DisRx 113 DisTx 113 DpIIEn 110 Dpllmd[1:0] 1 DSR 123 DsrAE 88-90 DSRChg 147 D S R od97 DSRzd 96	OCR Scan	PDF	CL-CD2431 MAP32

DPLL Search Results

DPLL Result Highlights (6)

DPLL Price and Stock

Renesas Electronics Corporation R5F10DPLLFB#H2G

STMicroelectronics EVL90WADP-LLCSR

Kyocera AVX Components CKR22CH150DP-LL

Renesas Electronics Corporation R5F10DPLLFB#X6G

Kyocera AVX Components CKR22CG270DP-LL

DPLL Datasheets Context Search

DS31408GN

CVPD-024

GR-1244-CORE

Untitled

ZL50011QCG1

ZL50010

Untitled

Untitled

Untitled

Untitled

APP4391

Untitled

GR-1244-CORE

GR-1244-CORE

GR-1244-CORE

GR-1244-CORE

ZL50018

Untitled

siemens sab 82532

siemens sab 82538

Untitled

Untitled

TS68950

MAP32