T10E
Abstract: 2b1q decoder
Text: Delta Sheet DS 5, 09.00 Quad ISDN 2B1Q Echocanceller Digital Front End DFE-Q V2.1 PEB/F 24911 Version 2.1 This Delta Sheet lists the add-on features and differences between the DFE-Q V2.1 and the DFE-Q V1.3. 1 Power Supply The DFE-Q V2.1 requires a +3.3 V ±0.3 V power supply. The inputs and outputs remain
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1111b)
0001b)
T10E
2b1q decoder
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Untitled
Abstract: No abstract text available
Text: MAX24101 15Gbps Octal Linear Equalizer General Description The MAX24101 restores high-frequency signal level at the decision-feedback equalizer DFE receiver for highloss backplane and cable channels. This permits the DFE receiver to meet BER goals. At 15Gbps, the MAX24101
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MAX24101
15Gbps
MAX24101
15Gbps,
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Untitled
Abstract: No abstract text available
Text: Decision Feedback Equalization in Stratix IV Devices AN-612-1.1 Application Note This application note describes the decision feedback equalization DFE feature found in the Stratix IV device equalizer. Use the DFE feature to improve the high frequency signal-to-noise ratio by compensating for inter-symbol interference (ISI).
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AN-612-1
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H6850
Abstract: PEF24911 24911H PEF24911H Q67233 PEF 24911 Q67230-H1234 Q67233-H1233
Text: P RODUCT B RIEF IEC4-Q PEF 24911 V2.1 DFE-Q & PEF 24902 V2.1 (AFE) ISDN Echocancellation Circuit 4-Channel for 2B1Q Line Code The widely used ISDN 4-channel chipset IEC4-Q consisting of the analog frontend PEB/F 24902 (AFE) and the digital frontend PEB/F 24911 (DFE-Q) has been
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B000-H0000-X-X-7600
H6850
PEF24911
24911H
PEF24911H
Q67233
PEF 24911
Q67230-H1234
Q67233-H1233
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10GBASE-LRM
Abstract: microcontroller pacemaker IQ2200 VSC8238 electronic dispersion compensator
Text: TRANSPORT PHYSICAL LAYER VSC8238 10.3125 Gbps Advanced Electronic Equalization with Limiting Amplifier, and Clock and Data Recovery BLOCK DIAGRAM: Initialization and Control Link Monitor Micro-Controller Interface Error Proxy VSC8238 VSC8238 FFE/DFE EQ Limiting Amplifier
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VSC8238
10GBASE-LRM
microcontroller pacemaker
IQ2200
VSC8238
electronic dispersion compensator
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10Gbase-kr backplane connector
Abstract: BCM8073 broadcom serdes data eye 1000BaseKX 10Gbase-kr transmitter LSI serdes CMOS CML 10G KR PHy 10GBASE-KR 1000BASE-KX Backplane 10Gbase KR
Text: BCM8073 Brief DUAL-CHANNEL SERIAL 10GBASE-KR TO XAUI TRANSCEIVER SUMMARY OF BENEFITS FEATURES • Two 10G-XAUI™ interfaces in one compact package • Targeted to meet the IEEE 802.3ap standard • High-performance DFE/FFE receive equalizer with full
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BCM8073
10GBASE-KR
10G-XAUITM
25G/10G
25-MHz
BCM8073
324-pin
8073-PB01-R
10Gbase-kr backplane connector
broadcom serdes data eye
1000BaseKX
10Gbase-kr transmitter
LSI serdes CMOS CML
10G KR PHy
1000BASE-KX Backplane
10Gbase KR
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bcm8071
Abstract: 1000BASE-KX Backplane 10G serdes 2.5 xaui 1000BaseKX 10G KR PHy 8b/10b encoder gearbox XAUI 1000BASE-X 4X CMU clock mhz
Text: BCM8071 SERIAL 10G BASE-KR TO XAUI BACKPLANE TRANSCEIVER SUMMARY OF BENEFITS FEATURES • New 10 GbE serial transceiver supporting high-bandwidth • Targeted to meet the draft IEEE 802.3ap standard backplane requirements • High performance DFE/FFE receive equalizer with full
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BCM8071
25-MHz
25-MHz
25/10G
BCM8071
8071-PB01-R
1000BASE-KX Backplane
10G serdes 2.5 xaui
1000BaseKX
10G KR PHy
8b/10b encoder
gearbox
XAUI
1000BASE-X
4X CMU clock mhz
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mark U1W
Abstract: V6DA DPA8 PEB 24901 SMD d1c smd diode D3B transistor SMD t05 CL15 aop 741 PEF24901
Text: ICs for Communications Quad ISDN 4B3T Echocanceller Digital Front End DFE-T V2.1 PEF 24901 Version 2.1 Preliminary Data Sheet 06.99 DS 1 • PEF 24901 Revision History: Current Version: 06.99 Previous Version: Page Page in previous (in current Version Version)
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DS125RT410
Abstract: No abstract text available
Text: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
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DS100RT410
SNLS448
DS100RT410
10GbE
48-pin,
DS125RT410
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DS125RT410
Abstract: No abstract text available
Text: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
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DS100RT410
SNLS448
DS100RT410
10GbE
DS100DF410
DS110RT410
DS110DF410
DS125RT410
DS125RT410
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Untitled
Abstract: No abstract text available
Text: Philips Semiconductors Preliminary specification ATSC 8-VSB Demodulator and Decoder PINNING • Feed forward including a decision feedback structure DFE • Range of -2.3 µs to +10.5 µs • Rate 2/3 (Rate 1/2 Ungerboeck code based) Reed-Solomon decoder
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TDA8960
QFP64
TDA8960.
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QSFP PCB design
Abstract: DS125RT410
Text: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
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DS100RT410
SNLS448
DS100RT410
10GbE
48-pin,
QSFP PCB design
DS125RT410
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CL15
Abstract: ST01 ST10 ST11 ST20 ST21 PEF24911 sr-atx delta PEF 2091 N V5.3
Text: ICs for Communications Quad ISDN 2B1Q Echocanceller Digital Front End DFE-Q V2.1 PEF 24911 Version 2.1 Preliminary Data Sheet 06.99 DS 1 • PEF 24911 Revision History: Current Version: 06.99 Previous Version: Page in previous Version Page (in current Version)
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QSFP
Abstract: DS125RT410
Text: DS100RT410 www.ti.com SNLS448 – JANUARY 2013 DS100RT410 Low Power 10GbE Quad Channel Retimer Check for Samples: DS100RT410 FEATURES – DS100RT410 EQ+CDR+DE : 10.3125 Gbps – DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps – DS110RT410 (EQ+CDR+DE): 8.5 - 11.3 Gbps
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DS100RT410
SNLS448
DS100RT410
10GbE
48-pin,
QSFP
DS125RT410
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1TR220
Abstract: No abstract text available
Text: P P RELIMINARY R O D U C T B R I E F IEC4-T PEF 24901 V2.1 DFE-T PEF 24902 V2.1 (AFE) ISDN Echocancellation Circuit 4-Channel for 4B3T Line Code The widely used ISDN 4-channel chipset IEC4-T consisting of the analog frontend PEB/F 24902 (AFE) and the digital frontend PEB/F 24901
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B115-H7865-X-X-7600
1TR220
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Transistor hall s41
Abstract: CEI-11G QSFP connector Xlaui 10 gbps transceiver board card fci tsmc design rule 40-nm QSFP QSFP 40G transceiver pcie gen3
Text: White Paper FPGAs at 40 nm and >10 Gbps: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers. These include the LC-based oscillator and decision-feedback equalization DFE at 40 nm for ultra-low jitter FPGA transceivers. Furthermore, the
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40G/100G
Transistor hall s41
CEI-11G
QSFP connector
Xlaui
10 gbps transceiver board
card fci
tsmc design rule 40-nm
QSFP
QSFP 40G transceiver
pcie gen3
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transistor SMD t05
Abstract: transistor t05 smd t05 package transistor pin configuration smd diode D3B ternary content addressable memory implementation for ternary content addressable PEB 2426 SMD d1c TS102080 mark U1W
Text: Da ta S he et, D S 1, S ep . 2 00 2 DFE-T V2.2 Quad ISDN 4B3T Echocanceller Digital Front End PEF 24901, Version 2.2 W i r ed Communications N e v e r s t o p t h i n k i n g . Edition 2002-09-30 Published by Infineon Technologies AG, St.-Martin-Strasse 53,
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D-81541
transistor SMD t05
transistor t05 smd
t05 package transistor pin configuration
smd diode D3B
ternary content addressable memory
implementation for ternary content addressable
PEB 2426
SMD d1c
TS102080
mark U1W
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V21-12
Abstract: T10E
Text: De lta She et, DS 9, No v. 2 00 1 DFE-Q V2.1 Quad ISDN 2B1Q Echocanceller Digital Front End PEF 24911 Version 2.1 Wi r ed Communications N e v e r s t o p t h i n k i n g . Edition 2001-11-08 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany
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D-81541
V21-12
T10E
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Untitled
Abstract: No abstract text available
Text: Data Sheet, DS 2, Nov. 2000 DFE-Q V2.1 Quad ISDN 2B1Q Echocanceller D ig i t a l F ro n t E n d P E F 2 4 9 1 1 V er s i o n 2 . 1 Wired Communication N e v e r s t o p t h i n k i n g . Edition 2000-11-23 Published by Infineon Technologies AG, St.-Martin-Strasse 53,
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D-81541
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SAFETY AWT 1 11
Abstract: ST30 ST01 ST10 ST11 ST20 ST21 ST31 Slot-1 MON8
Text: Delta She et, DS 2, Ju ne 2001 DFE-T V2.1 Quad ISDN 4B3T Echocanceller D ig i t a l F ro n t E n d P E F 2 4 9 0 1 V er s i o n 2 . 1 Wired Communications N e v e r s t o p t h i n k i n g . Edition 2001-06-22 Published by Infineon Technologies AG, St.-Martin-Strasse 53,
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D-81541
1111b)
0001b)
SAFETY AWT 1 11
ST30
ST01
ST10
ST11
ST20
ST21
ST31
Slot-1
MON8
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G1D32
Abstract: "Hard Disk Drive" preamplifier hard disk head preamp DFE9952R mts servo controller EQUALIZER "DOWN SAMPLER" FILTER TAP coefficients ADAPTIVE EQUALIZER "DOWN SAMPLER" FILTER TAP coefficients adaptive equalizer error filter down sampler adaptive equalizer circuit down sampler DC50K
Text: Ob|ectlve Specification Philips Semiconductors DFE Read Signal Processor DFE9952R GENERAL DESCRIPTION The DFE9952R is a 200 Mbit/s Decision Feedback Equalization DFE read channel integrated circuit designed for hard disk drives. With enhanced decision feedback equalization implemented with advanced BiCMOS technology, the
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DFE9952R
DFE9952R
OT314-2
711002b
G1D32
"Hard Disk Drive" preamplifier
hard disk head preamp
mts servo controller
EQUALIZER "DOWN SAMPLER" FILTER TAP coefficients
ADAPTIVE EQUALIZER "DOWN SAMPLER" FILTER TAP coefficients
adaptive equalizer error filter down sampler
adaptive equalizer circuit down sampler
DC50K
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Untitled
Abstract: No abstract text available
Text: ICs for Communications Quad ISDN 2B1Q Echocanceller Digital Front End DFE-Q V2.1 PEF 24911 Version 2.1 Preliminary Data Sheet 06.99 PEF 24911 Revision History: Current Version: 06.99 Previous Version: Page in previous Version Page (in current Version) Subjects (major changes since last revision)
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Untitled
Abstract: No abstract text available
Text: SIEMENS ICs for Communications Quad ISDN 2B1Q Echocanceller Digital Front End Quad IEC DFE-Q PEB 24911 Version 1.2 PEF 24911 Version 1.2 Datasheet 12.97 DS 1 PEB 24911 Revision History: Original Version: Previous Releases: none Page Subjects changes since last revision
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80-kHz
Cl64x
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Untitled
Abstract: No abstract text available
Text: ICs for Communications Quad ISDN 4B3T Echocanceller Digital Front End DFE-T V2.1 PEF 24901 Version 2.1 Preliminary Data Sheet 06.99 PEF 24901 Revision History: Current Version: 06.99 Previous Version: Page in previous Version Page (in current Version) Subjects (major changes since last revision)
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120-kHz
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