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    DECADE COUNTER WITH PHASE-PULSE DATA REPRESENTATION Search Results

    DECADE COUNTER WITH PHASE-PULSE DATA REPRESENTATION Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    NFM15PC755R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    NFM15PC435R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    NFM15PC915R0G3D Murata Manufacturing Co Ltd Feed Through Capacitor, Visit Murata Manufacturing Co Ltd
    D1U54T-M-2500-12-HB4C Murata Manufacturing Co Ltd 2.5KW 54MM AC/DC 12V WITH 12VDC STBY BACK TO FRONT AIR Visit Murata Manufacturing Co Ltd
    GRJ43DR7LV224KW01K Murata Manufacturing Co Ltd Chip Multilayer Ceramic Capacitors with Soft Termination for General Purpose Visit Murata Manufacturing Co Ltd

    DECADE COUNTER WITH PHASE-PULSE DATA REPRESENTATION Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546 − OCTOBER 2003 D Qualification in Accordance With D D D D D D D D D Significant Power Reduction Compared to AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


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    CD74HC4017Q1 SCLS546 AEC-Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017EP SCLS550 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546 − OCTOBER 2003 D Qualification in Accordance With D D D D D D D D D Significant Power Reduction Compared to AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


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    CD74HC4017Ä SCLS546 AEC-Q100â PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546 − OCTOBER 2003 D Qualification in Accordance With D D D D D D D D D Significant Power Reduction Compared to AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


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    CD74HC4017Q1 SCLS546 AEC-Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546 − OCTOBER 2003 D Qualification in Accordance With D D D D D D D D D Significant Power Reduction Compared to AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


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    CD74HC4017Q1 SCLS546 AEC-Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017Ä SCLS550 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 D D D D D D D D D 4.5-V to 5.5-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times Direct LSTTL Input Logic Compatibility


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    CD54HCT4017 SGDS012 CD54HCT4017 PDF

    CD54HCT4017

    Abstract: CD54HCT4017F3A
    Text: CD54HCT4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS012 – MAY 1999 D D D D D D D D D 4.5-V to 5.5-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times Direct LSTTL Input Logic Compatibility


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    CD54HCT4017 SGDS012 CD54HCT4017 CD54HCT4017F3A PDF

    Untitled

    Abstract: No abstract text available
    Text: CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30%


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    CD54HC4017 SGDS011 PDF

    8601101EA

    Abstract: CD54HC4017 CD54HC4017F3A
    Text: CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30%


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    CD54HC4017 SGDS011 CD54HC4017 8601101EA CD54HC4017F3A PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking


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    CD74HC4017-Q1 SCLS546SA PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017EP SCLS550 PDF

    CD74HC4017

    Abstract: CD74HC4017QM96EP CD74HC4017QPWREP MTSS001C HC4017E
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017EP SCLS550 CD74HC4017 CD74HC4017QM96EP CD74HC4017QPWREP MTSS001C HC4017E PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017EP SCLS550 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking


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    CD74HC4017-Q1 SCLS546SA CD74HC4017 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017Ä SCLS550 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017ĆEP HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS550 − DECEMBER 2003 D Controlled Baseline D D D D D D D D D D Fanout Over Temperature Range − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of


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    CD74HC4017EP SCLS550 PDF

    SCLS546

    Abstract: texas ttl data book AEC-Q100 CD74HC4017 CD74HC4017QM96Q1 CD74HC4017QPWRQ1 MTSS001C Q100
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546 − OCTOBER 2003 D Qualification in Accordance With D D D D D D D D D Significant Power Reduction Compared to AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control


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    CD74HC4017Q1 SCLS546 AEC-Q100 texas ttl data book AEC-Q100 CD74HC4017 CD74HC4017QM96Q1 CD74HC4017QPWRQ1 MTSS001C Q100 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking


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    CD74HC4017-Q1 SCLS546SA CD74HC4017 PDF

    LS490

    Abstract: SN54LS490 SN54LS90 SN74LS490 SN74LS490N SN74LS90 1N3064 SN74LS90 Decade Counter texas instruments
    Text: SN54LS490, SN74LS490 DUAL 4-BIT DECADE COUNTERS SDLS125A – OCTOBER 1976 – REVISED JULY 1998 D D D D 1CLK 1CLR 1QA 1SET9 1QB 1QC 1QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2CLK 2CLR 2QA 2SET9 2QB 2QC 2QD SN54LS490 . . . FK PACKAGE TOP VIEW description


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    SN54LS490, SN74LS490 SDLS125A SN54LS490 LS490 SN54LS490 SN54LS90 SN74LS490 SN74LS490N SN74LS90 1N3064 SN74LS90 Decade Counter texas instruments PDF

    CD74HC4017

    Abstract: CD74HC4017QM96G4Q1 CD74HC4017QM96Q1 CD74HC4017QPWRQ1 MTSS001C
    Text: CD74HC4017ĆQ1 HIGHĆSPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking


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    CD74HC4017Q1 SCLS546SA CD74HC4017 CD74HC4017QM96G4Q1 CD74HC4017QM96Q1 CD74HC4017QPWRQ1 MTSS001C PDF

    Untitled

    Abstract: No abstract text available
    Text: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking


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    CD74HC4017-Q1 SCLS546SA CD74HC4017 PDF

    Untitled

    Abstract: No abstract text available
    Text: CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30%


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    CD54HC4017 SGDS011 PDF

    CD54HC162

    Abstract: CD54HC162F3A CD54HC160 CD54HC160F3A
    Text: CD54HC160, CD54HC162 BCD SYNCHRONOUS DECADE COUNTERS SCHS301 – JUNE 2000 D D D D D D D D Synchronous Counting and Loading Two Count-Enable Inputs for n-Bit Cascading Asynchronous Reset CD54HC160 Synchronous Reset (CD54HC162) Look-Ahead Carry for High-Speed Counting


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    CD54HC160, CD54HC162 SCHS301 CD54HC160) CD54HC162) CD54HC162 CD54HC162F3A CD54HC160 CD54HC160F3A PDF