PXB 4325
Abstract: EN16 TQFP-144 DAT-16 DAT16
Text: ICs for Communications Content Addressable Memory Element CAME PXB 4360 F Version 1.1 Preliminary Data Sheet 10.97 DS 1 PXB 4360 F CONFIDENTIAL Revision History: Previous Version: Page Page in previous (in current Version Version) Current Version: 10.97
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diode T35 12H
Abstract: T35 12H ac power adapter for notebook schematic GAL programmer schematic 7313 28 pin automatic water level controller circuit diagram PCnet32 remote control gate sytem bel 187 bel 187 transistor diagram
Text: PRELIMINARY Am79C965 PCnet -32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for 486 and Video Electronics Standards Association VESA local buses ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and Ethernet standards
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Am79C965
PCnetTM-32
32-Bit
Am486TM
Am7990
Am79C90
Am79C960
Am79C961
Am79C961A
Am79C970A
diode T35 12H
T35 12H
ac power adapter for notebook schematic
GAL programmer schematic
7313 28 pin
automatic water level controller circuit diagram
PCnet32
remote control gate sytem
bel 187
bel 187 transistor diagram
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1F0H-1F7H configuration pio
Abstract: S3 TRIO 64 HT6560A HT6560B DAT00 6560B DD15 LD11 LD12 LD04
Text: HT6560B Enhanced VL_Bus IDE Controller Features • • • • • • • • Pin-to-pin backward compatible with HT6560A VL_Bus IDE controller IDE interface to 486 and 386 DX/SX local bus VESA VL_Bus rev 1.0 compatible Connects directly to VL_Bus and IDE interface, no extra TTL needed
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HT6560B
HT6560A
HT-6560B/C
CS37XN
1F0H-1F7H configuration pio
S3 TRIO 64
HT6560B
DAT00
6560B
DD15
LD11
LD12
LD04
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D103 TCO
Abstract: en1 3007 altera rgmii specification Automated Guided Vehicles project clock tree guidelines RGMII constraints AN432 D101 D102 D103
Text: AN 545: Design Guidelines and Timing Closure Techniques for HardCopy ASICs July 2010 AN-545-2.1 This application note covers topics from a timing closure perspective, for the successful migration to HardCopy ASICs from Altera’s FPGAs. The first section
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AN-545-2
D103 TCO
en1 3007
altera rgmii specification
Automated Guided Vehicles project
clock tree guidelines
RGMII constraints
AN432
D101
D102
D103
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Untitled
Abstract: No abstract text available
Text: 3.3 VOLT M13 MULTIPLEXER IDT82V8313 Version 2 March 15, 2004 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • • FAX: (408) 492-8674 Printed in U.S.A. 2004 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
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IDT82V8313
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CLK12
Abstract: IDT82V8313 MX12 MX23 GR 733 512 CJ3
Text: 3.3 VOLT M13 MULTIPLEXER IDT82V8313 Version 1 December 15, 2003 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • • FAX: (408) 492-8674 Printed in U.S.A. 2003 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
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IDT82V8313
CLK12
IDT82V8313
MX12
MX23
GR 733
512 CJ3
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power generation POWER COMMAND HM 1211
Abstract: POWER COMMAND HM 1211 manual POWER COMMAND HM 1211 PM19 Package D-18 DSP56300 DSP56305 BRF6
Text: Freescale Semiconductor, Inc. Addendum DSP56305UMAD/D Rev. 1, 11/2002 DSP56305 User’s Manual Addendum Freescale Semiconductor, Inc. CONTENTS 1 Introduction .1 2 Modified Signal Definitions .1 3 Operating Mode Register OMR
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DSP56305UMAD/D
DSP56305
power generation POWER COMMAND HM 1211
POWER COMMAND HM 1211 manual
POWER COMMAND HM 1211
PM19 Package
D-18
DSP56300
BRF6
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K30A transistor
Abstract: POWER COMMAND HM 1211 manual K30A POWER COMMAND HM 1211 power generation POWER COMMAND HM 1211 DSP56301V HM 1211 transistor k30a B-28 DSP56300
Text: DSP56301 USER’S MANUAL DSP56301UM Rev. 4, November 2005 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224
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DSP56301
DSP56301UM
CH370
16-bit
24-bit
Index-15
Index-16
K30A transistor
POWER COMMAND HM 1211 manual
K30A
POWER COMMAND HM 1211
power generation POWER COMMAND HM 1211
DSP56301V
HM 1211
transistor k30a
B-28
DSP56300
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lg crt monitor circuit diagram
Abstract: hs 8109 DS-17 SANYO 486dx isa bios pin assignment SP1137 hitachi plasma electronic diagram sharp lm64p DS-18 SANYO Spectrol 157 74 VGA 20 PIN LCD MONITOR CABLE CONNECTION DIAGRAM
Text: SPC8110 LOCAL BUS LCD/CRT VGA CONTROLLER Technical Manual Issue Date: 04/01/97 Document Office No. X07-GQ-001-01 Copyright 1997 S-MOS Systems Inc. All rights reserved. VDC This document, and any text derived, extracted or transmitted from it, is the sole property of S-MOS Systems Inc. and may not be used, copied,
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SPC8110
X07-GQ-001-01
LM334
X07-GG-002-01
lg crt monitor circuit diagram
hs 8109
DS-17 SANYO
486dx isa bios pin assignment
SP1137
hitachi plasma electronic diagram
sharp lm64p
DS-18 SANYO
Spectrol 157 74
VGA 20 PIN LCD MONITOR CABLE CONNECTION DIAGRAM
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D11010
Abstract: SDCUV6482 D11010KFCS LD11 LD12 MPC8260 MPC947 DIN41612 128 D25-CRCW1206 SDRAM16M
Text: 12/17/01 Rev 0.1 WITH MPC8266ADS - PCI User’s Manual Board Rev. PROTOTYPE-B Semiconductor Products Sector Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can
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MPC8266ADS
D11010
SDCUV6482
D11010KFCS
LD11
LD12
MPC8260
MPC947
DIN41612 128
D25-CRCW1206
SDRAM16M
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60nd02
Abstract: D0798 D05103 50MHZ S2020 S2021 d2059 DAT02 DAT06 DAT04
Text: DEVICE HIPPI SPECIFICATION SOURCE/DESTINATION INTERFACE CIRCUITS HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS FEATURES S2020/S2021 HIPPI Chipset • Functionally compliant with the ANSI HIPPI standard • 32-Bit data channel • Equivalent single channel rate of 800 Mbits/sec
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S2020/S2021
32-Bit
16-Bit
600ns,
400ns
60nd02
D0798
D05103
50MHZ
S2020
S2021
d2059
DAT02
DAT06
DAT04
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K30A transistor
Abstract: K30A 1 HP25 731 motorola transistor k30a Nippon capacitors
Text: DSP56301 User’s Manual 24-Bit Digital Signal Processor DSP56301UM/AD Revision 2.0, August 1999 OnCE and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other trademarks are those of their respective owners.
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DSP56301
24-Bit
DSP56301UM/AD
Index-17
Index-18
K30A transistor
K30A
1 HP25
731 motorola
transistor k30a
Nippon capacitors
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DAT29
Abstract: MCD15 dat18 ADR30 1-5R56 ADR27 Dat21 MBD14 MCD4 DK6554X
Text: MALE HEADER FOR CONNECTION OF 6554X DAUGHTER CARD PFP CARRIER . VPIA[0.23] MEMORY INTERFACE GVCC MAD[0.15] VPIA[0.23] VESA CONNECTOR MAD[0.15] VPID[0.31] R29 VPID[0.31] AA[0.8] 20K P3 VPIA0 A39 -BE1 A41 -RD 11 -RDYRTN 23 -RD BE1 -RDYRTN CCLK A42 BE2
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6554X
VPIA10
DAT16
DAT21
ADR22
DAT22
ADR23
DAT24
ADR25
DAT25
DAT29
MCD15
dat18
ADR30
1-5R56
ADR27
Dat21
MBD14
MCD4
DK6554X
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B-26
Abstract: DSP56301 DSP56L307 DAT18 DIR12
Text: Freescale Semiconductor, Inc. Addendum DSP56301UMAD/D Rev. 3, 5/2003 DSP56301 User’s Manual Addendum Freescale Semiconductor, Inc. CONTENTS 1 Introduction.1 2 Modified Signal Definitions.1 3 Operating Mode Register OMR Definition.3
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DSP56301UMAD/D
DSP56301
DSP56301UM/D)
DSP56301UMAD/D,
B-26
DSP56L307
DAT18
DIR12
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2am SMD
Abstract: DAT16 DAT28
Text: ICs for Communications Content Addressable Memory Element CAME PXB 4360 F Version 1.1 Data Sheet 07.2000 Version 1.1 3;% 5HYLVLRQ +LVWRU\ &XUUHQW 9HUVLRQ Previous Version: Preliminary Data Sheet 11.97 DS 2) Page Page Subjects (major changes since last revision)
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S3 TRIO 64
Abstract: HT6560A DD15 LA15 LD01 LD31 HC11111 ld18 DAT02 DAT06
Text: HT6560A VL_Bus IDE Controller Features • • • • • • VESA VL_Bus rev 1.0 compatible. Connects directly to VL_Bus and IDE interface no extra TTL needed. Supports 16 bits and 32 bits data transfer. Zero wait_state 50MHz operation. Support read pre-fetch, posted write and I/O
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HT6560A
50MHz
100-pin
11111VY33SLDDDT2D222
12345NN10SK589N96876
HT-6560A
S3 TRIO 64
HT6560A
DD15
LA15
LD01
LD31
HC11111
ld18
DAT02
DAT06
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ADR05
Abstract: 50 pins ide connector S3 TRIO 64 1F0H-1F7H ADR30 vl-bus ide controller DAT12 LD31 ADR27
Text: HT — 6560A VL_BUS IDE CONTROLLER JAN.04.1994 PAGE: A. General Description — HT–6560A is a VL_Bus IDE controller which provides a control logic and data path between 486, 386 VL_Bus and IDE drives. The HT–6560A is fully compatible with the ANSI ATA revision 3.0 specification for IDE hard disk operation
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PCnet32
Abstract: LADR2 smd transistor marking code EY ST7032 PQJ160 PQR160 79c965 S8-A marking AM486TM SMD MARKING CODE t2x
Text: Am79C965A PCnet -32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet controller for 486 and Video Electronics Standards Association VESA local buses ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and Ethernet standards
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Am79C965A
PCnetTM-32
32-Bit
136-byte
128-byte
Am486TM
Am186,
Am386,
Am486,
Am29000
PCnet32
LADR2
smd transistor marking code EY
ST7032
PQJ160
PQR160
79c965
S8-A marking
SMD MARKING CODE t2x
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SH 6770
Abstract: No abstract text available
Text: 1.0 Product Description 1.1 Overview The B t8 2 l5 is a bidirectional buffer with a 36-bit bidirectional port and 9-bit uni directional ports that can be configured to transfer iixed-length cells. Bach direc tion can store up to 512 36-bit words. This part, therefore, replaces eight
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36-bit
32-bit-wide
100-pin
Bt8215
L821501
SH 6770
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79c965
Abstract: AMD 79c97* lance
Text: a P R E L IM IN A R Y Advanced Micro Devices Am79C965 PCnet -32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHARACTERISTICS • Single-chip Ethernet con tro ller for 486 and V ideo Electronics Standards Association VESA local buses ■ Supports ISO 8802-3 (IEEE/ANSI 802.3) and
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Am79C965
32-Bit
Am486â
PCnet-32
79C965
79c965
AMD 79c97* lance
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wd9710
Abstract: MRC D30
Text: W D 9710 Fully Integrated 64-Bit Graphics and Motion Video Accelerator Data Book Publication ID: 7 9 -8 9 0 0 1 8-0 00 -P 3 Publication Date: March 1, 1 9 9 5 Company: WESTERN DIGITAL CORP This title page is provided as a service by In form ation Handling S ervices and displays
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64-Bit
79-890018-000-P3
171fl22a
WD9710
208-pin
200-PIN
wd9710
MRC D30
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DAT46
Abstract: No abstract text available
Text: Preliminary SME5431 PCI-360 SME5434PCI-440 SME5434PCI-480 m icrosystem s March 1999 UltraSPARC -!!/ CPU Module DATA SHEET 360/440/480M H z CPU; 0.25 to 2 MB L2 cache, UPA64S, 66M Hz PCI D e s c r ip t io n The SME5431PCI and SME5434PCI UltraSPARC™-IIi CPU Modules provide high-performance, SPARC v9
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SME5431
PCI-360
SME5434PCI-440
SME5434PCI-480
360/440/480M
UPA64S,
SME5431PCI
SME5434PCI
SME1430
DAT46
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Untitled
Abstract: No abstract text available
Text: Prelim in ary SME1040 S un M ic r o e l e c t r o n ic s Ju ly 1997 UltraSPARC -lli DATA SHEET Highly Integrated 64-Bit RISC Processor, PCI Interface F u n c t io n a l D e s c r ip t io n U ltra S P A R C -II¿ SM E1040 is a highly-integrated 64-bit SP A R C V9 superscalar processor. A n optional A P B ™
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SME1040
64-Bit
E1040)
SME2411)
EDATA-20
EDATA-25
EDATA-51
EDATA-54
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805-0086-02
Abstract: H05U E22M UltraSPARC ii SME2411
Text: P r e li m in a n 7 SM E1040 S un M i c r o e l e c t r o n i c s Ju ly 1997 UltraSPARC -lli D ATA SHEET H ig h ly Integrateci 64-Bit RISC Processor, PCI Interface F u n c t io n a l D e s c r ip t io n U ltra S P A R C - II/ SM E1 0 4 0 is a h ig h ly- in teg ra te d 64-bit S P A R C V 9 su p e rsca la r processor. A n o p tio n a l A P B ™
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E1040
64-Bit
E2411)
SME1040BGA-266
SME1040BGA-300
300MHz
805-0086-02
H05U
E22M
UltraSPARC ii
SME2411
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