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    80386SX

    Abstract: DIP48 MK5025 MK5027 MK50H25 Z8000 dali Receiver 80286 instruction
    Text: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst


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    PDF MK50H25 MK50H25 MK5025 25/LAPD) MK5027 MK5029 80386SX DIP48 MK5025 MK5027 Z8000 dali Receiver 80286 instruction

    mk5021

    Abstract: N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI
    Text: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 mk5021 N393 BCNT DIP48 MK5027 MK50H28 PLCC52 Z8000 A 1905 LMI

    N393

    Abstract: DIP48 MK50H25 MK50H27 MK50H28 PLCC52 Z8000 DAL13
    Text: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 N393 DIP48 MK50H25 MK50H27 MK50H28 PLCC52 Z8000 DAL13

    JT-Q703

    Abstract: MK50H27Q-33 bsnt1
    Text: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements


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    PDF MK50H27 JT-Q703 MK50H25 25/LAPD) MK50H29 MK50H28 MK50H27 MK50H27TQ33B MK50H27Q-33 bsnt1

    Q703

    Abstract: DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703 68000 thomson
    Text: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements


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    PDF MK50H27 JT-Q703 MK50H25 25/LAPD) MK50H29 MK50H28 MK50H27 Q703 DIP48 MK50H25 Z8000 68000 thomson

    DIP48

    Abstract: MK5021 MK5027 MK50H28 PLCC52 Z8000
    Text: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 DIP48 MK5021 MK5027 MK50H28 PLCC52 Z8000

    DIP48

    Abstract: MK50H25 MK50H27 MK50H28 PLCC52 Z8000 BCNT
    Text: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent Mode (no LMI Protocol


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 DIP48 MK50H25 MK50H27 MK50H28 PLCC52 Z8000 BCNT

    uav design specification

    Abstract: water filling station circuit diagram DALI CONTROL logical block diagram of 80286 uav electronic design water level controller using timer 555 8086 microprocessor pin description control data bus for 80286 uav design z80 cio
    Text: MK50H25 HIGH SPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted On chip DMA control with programmable burst


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    PDF MK50H25 MK50H25 MK5025 25/LAPD) MK5027 MK5029 uav design specification water filling station circuit diagram DALI CONTROL logical block diagram of 80286 uav electronic design water level controller using timer 555 8086 microprocessor pin description control data bus for 80286 uav design z80 cio

    IN5048

    Abstract: Q703 DIP48 MK50H25 MK50H27 MK50H28 Z8000 JT-Q703
    Text: MK50H27 Signalling System 7 Link Controller SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements


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    PDF MK50H27 JT-Q703 MK50H25 25/LAPD) MK50H29 MK50H28 MK50H27 IN5048 Q703 DIP48 MK50H25 Z8000

    TSCT 2300

    Abstract: 48-PIN DIP48 MK5025 MK5027 PLCC52 Z8000 DALI BASIC SO LSI-11
    Text: MK5027 SS7 SIGNALLING LINK CONTROLLER CMOS FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T,


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    PDF MK5027 10MHz. 48-PIN MK5025) MK5032) TSCT 2300 DIP48 MK5025 MK5027 PLCC52 Z8000 DALI BASIC SO LSI-11

    Untitled

    Abstract: No abstract text available
    Text: MK50H28 MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 Annex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits PVCs . Optional Transparent (or no LMI/LIV Protocol


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393

    dale r01f

    Abstract: MK68H MK68590 r01f dale MK68200 Z8000 MOSTEK ROM r01f mostek MK5025 IN914
    Text: MK5025 P R E L IM IN A R Y C O M M U N IC A T IO N S PR O O U C TS FEATURES DAL04 £ £ 3 £ 4 £ S £ Z Data rate up to 7 MBPS with 64 bytes FIFOs in each direction. DAL03 6 C DA102 7 DAL01 1 H Z Complete Date Link Layer Implementation. DALDQ £ £ 11 £


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    PDF 48-pin MK68590) MK5027) MK5025 dale r01f MK68H MK68590 r01f dale MK68200 Z8000 MOSTEK ROM r01f mostek MK5025 IN914

    Untitled

    Abstract: No abstract text available
    Text: A m 79C 900 In t e g r a te d L o c a l A re a C o m m u n ic a tio n s C ontroller ILACC™ Distinctive Characteristics. 1-51 General Description. 1-51


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    PDF X777777 Am79C900

    47C241N

    Abstract: BM11100 47c231an 47c241 BM11103 IC TB 1237 AN BM1152 tmp*47c443n TLCS-470 TMP47C840N
    Text: TOSHIBA W 1 3 ^ 7 y n - ^ 3 T < ^ 7 P = i> ^ - t 0z L - ^ B a ^ í f i t - o i 'T h * tt ¿L mili *-4 - ' » f t 7 V f* ü f § « ü y V 7 7 > H f§ f§ ÿ ± r ' ^ y ¿r 'y V b V W- 7 > H J£ W S ; w S f t fk £ W i E S f f r S / C V S f£ 7 H i 7 E S fS ÍÉ ÍI^ #


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    PDF 5O40iii 47P452VN/F SDIP42/QFP44 BM1120/BM1121 TMP47 C452BN/F TMP47P453VN/F 47C241N BM11100 47c231an 47c241 BM11103 IC TB 1237 AN BM1152 tmp*47c443n TLCS-470 TMP47C840N

    mk7990

    Abstract: MK5021Q10 marking r01f mk5027q10 CSR 41b datasheet SMD R01f 48-PIN MK5025 PLCC52 mk5021
    Text: • 7^21237 D OMSa ^a 3ñT M S G T H SGS-THOMSON _ MK5025 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A . CMOS ■ FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE


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    PDF D04S3T3 MK5025 16-BIT 10MHz 64-BYTE 48-PIN MK7990) DD45432 mk7990 MK5021Q10 marking r01f mk5027q10 CSR 41b datasheet SMD R01f MK5025 PLCC52 mk5021

    SRS 4451

    Abstract: No abstract text available
    Text: / = T S G S -T H O M S O N MK50H25 HIGHSPEED LINK LEVEL CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25- 16). ■ Data rate up to 20 Mbps continuous (MK50H25 - 33) or up to 51 Mbps bursted


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    PDF MK50H25 MK50H25 MK50H25- MK5025 25/LAPD) MK5027 MK5029 SRS 4451

    Untitled

    Abstract: No abstract text available
    Text: /= 7 ^ 7 # . S G S -T H O M S O N MK50H28 [fö i] D ^ © [i[L [l© T O R ! ]D © i MULTI LOGICAL LINK FRAME RELAY CONTROLLER ADVANCE DATA SECTION 1 - FEATURES • Based on ITU Q.933 Annex A and T1.617 An­ nex D Standards for Frame Relay Service and


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    PDF MK50H28 nT1/T391, nT2/T392, nN1/N391, nN2/N392, nN3/N393 00714fib

    MK7990

    Abstract: TSW 8088 mk5021q10
    Text: SGS-THOMSON ^ D Û ^ O llL C l'Ê r ^ Q iD 'Ê l M K 5 0 2 5 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A • CMOS . FULLY COM PATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE


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    PDF 16-BIT 10MHz 64-BYTE 48-PIN MK7990) DIP48 600-M PLCC52 K502510/02 K5021Q10/0 MK7990 TSW 8088 mk5021q10

    MK50250

    Abstract: 00-OF dali power supply circuit diagram
    Text: T 'is s a ? □Gsob'ìa t S G S -T H O M S O N g ì P 7 5 -ll-3 2 > MK5025 M O œ iU lO ïiT O iQ Û S 3GE S G S-THOMSON D CCITT X.25 LINK LEVEL CONTROLLER P R E LIM IN A R Y DATA CMOS FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz


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    PDF MK5025 16-BIT 10MHz 64-BYTE 48-PIN MK5032) K5025Q MK50250 00-OF dali power supply circuit diagram

    Untitled

    Abstract: No abstract text available
    Text: £ jj SGS-THOMSON ¡HJOTTIfMOOi MK5027 SS7 SIGNALLING LINK CONTROLLER • CMOS . FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATA RATE UP TO 2.5Mbps FOR SS7 PROTO­ COL PROCESSING , 7Mbps FOR TRANSPAR­ ENT HDLC MODE ■ COMPLETE LEVEL 2 IMPLEMENTATION


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    PDF MK5027 10MHz 48-PIN MK5025) MK5032) MK5027 BUDOB5H1ILI1ISTO08Ã

    Untitled

    Abstract: No abstract text available
    Text: SGS-THOMSON ü * fô H H d g ïï[iM D ( g ! M K 5 0 2 5 CCITT X.25 LINK LEVEL CONTROLLER P R E L IM IN A R Y D A T A • CMOS ■ FULLY COM PATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS . SYSTEM CLOCK RATE TO 10MHz ■ DATE RATE UP TO 7Mbps, WITH A 64-BYTE


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    PDF 16-BIT 10MHz 64-BYTE 48-PIN MK7990) PLCC52 MK502510/02 MK5021Q10/0 MK5027P10/0

    Untitled

    Abstract: No abstract text available
    Text: 7^2^237 0045434 725 • SGTH SGS-THOMSON MK5027 SS7 SIGNALLING LINK CONTROLLER ■ CMOS ■ FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS ■ SYSTEM CLOCK RATE TO 10MHz ■ DATA RATE UP TO 2.5Mbps FOR SS7 PROTO­ COL PROCESSING , 7Mbps FOR TRANSPAR­ ENT HDLC MODE


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    PDF MK5027 10MHz 48-PIN MK5025) MK5032) MK5027 600ns 100ns K5027

    Untitled

    Abstract: No abstract text available
    Text: r= 7 * • 1 /, S G S 'T H O M S O N MK50H25 M is œ U E ig T M O e i HIGHSPEED LINK LEVEL CONTROLLER AD VA N C E DATA SECTION 1 - FEATURES • System clock rate up to 33 MHz MK50H25 33 , 25 MHz (MK50H25 - 25), or 16 MHz (MK50H25 - 16). ■ Data rate up to 20 Mbps continuous


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    PDF MK50H25 MK50H25 MK50H25- MK5025 EROMD07 EROMD05 DAL15 DAL14

    AM79C900

    Abstract: 80X86 10s9 AM79C900JC AMD 29000
    Text: Am79C900 Integrated Local Area Com m unications Controller I LACC Distinctive C h a ra cte ristics. 1-51 G eneral D e s c rip tio n .1-51


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    PDF Am79C900 80X86 10s9 AM79C900JC AMD 29000