D917 Search Results

D917 Price and Stock

Filter by Manufacturer


Analog Devices Inc AD9172BBPZ IC RF DAC 144BGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	AD9172BBPZ	Tray	10		1	1 $380.41 10 $380.41 100 $380.41 1000 $380.41 10000 $380.41	Buy Now
Mouser Electronics	AD9172BBPZ		13			1 $411.95 10 $380.42 100 $380.42 1000 $380.42 10000 $380.42	Buy Now
Newark	AD9172BBPZ	Bulk	1		1	1 $411.95 10 $380.42 100 $380.42 1000 $380.42 10000 $380.42	Buy Now
Richardson RFPD	AD9172BBPZ				1	1 $413.89 10 $392.93 100 $388.02 1000 $388.02 10000 $388.02	Buy Now
Win Source Electronics	AD9172BBPZ		176			1 $366.1972 10 $366.1972 100 $366.1972 1000 $366.1972 10000 $366.1972	Buy Now
Analog Devices Inc AD9174BBPZ IC RF DAC 144BGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	AD9174BBPZ	Tray	6		1	1 $760.86 10 $760.86 100 $760.86 1000 $760.86 10000 $760.86	Buy Now
Mouser Electronics	AD9174BBPZ		4			1 $778.91 10 $760.87 100 $760.87 1000 $760.87 10000 $760.87	Buy Now
Newark	AD9174BBPZ	Bulk	2		1	1 $778.91 10 $760.86 100 $760.86 1000 $760.86 10000 $760.86	Buy Now
Panduit Corp CD9-17B DIEINSERT,CA9APPLICATOR,17B,YL,E
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CD9-17B	Bulk	4		1	1 $603.88 10 $603.88 100 $545.0184 1000 $545.0184 10000 $545.0184	Buy Now
Avnet Americas	CD9-17B	Bulk		8 Weeks	1	1 $495.6875 10 $495.6875 100 $495.6875 1000 $495.6875 10000 $495.6875	Buy Now
Newark	CD9-17B	Bulk			1	1 $725.69 10 $678.1 100 $590.86 1000 $590.86 10000 $590.86	Buy Now
Sager	CD9-17B				1	1 $508.4 10 $489.57 100 $483.6 1000 $483.6 10000 $483.6	Buy Now
Analog Devices Inc AD9171BBPZ IC RF DAC 144BGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	AD9171BBPZ	Tray	4		1	1 $193.88 10 $193.88 100 $188.625 1000 $188.625 10000 $188.625	Buy Now
Mouser Electronics	AD9171BBPZ		5			1 $193.88 10 $188.61 100 $188.59 1000 $188.59 10000 $188.59	Buy Now
Newark	AD9171BBPZ	Bulk	1		1	1 $216.43 10 $188.62 100 $188.62 1000 $188.62 10000 $188.62	Buy Now
Analog Devices Inc	AD9171BBPZ		74			1 $223.26 10 $188.625 100 $188.625 1000 $140.06 10000 $140.06	Buy Now
Rochester Electronics	AD9171BBPZ		687		1	1 $209.58 10 $209.58 100 $197.01 1000 $178.14 10000 $178.14	Buy Now

Richardson RFPD	AD9171BBPZ				3	1 - 10 $194.83 100 $192.4 1000 $192.4 10000 $192.4	Buy Now
Analog Devices Inc AD9177BBPZ QUAD 16-BIT, 12GSPS RFDAC WITH D
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	AD9177BBPZ	Tray	3		1	1 $1115.96 10 $1115.96 100 $1115.96 1000 $1115.96 10000 $1115.96	Buy Now
Mouser Electronics	AD9177BBPZ		5			1 $1193.84 10 $1193.84 100 $1193.84 1000 $1193.84 10000 $1193.84	Buy Now
Newark	AD9177BBPZ	Bulk			1	1 $1115.96 10 $1115.96 100 $1115.96 1000 $1115.96 10000 $1115.96	Buy Now
Richardson RFPD	AD9177BBPZ				1	1 $1214.17 10 $1152.69 100 $1138.28 1000 $1138.28 10000 $1138.28	Buy Now

Find more D917 price and stock on Findchips.com

D917 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
IS61QDB22M36 Abstract: D0-35 IS61QDB24M18 Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered	Original	IS61QDB22M36-300M3 IS61QDB22M36-300M3L IS61QDB24M18-300M3 IS61QDB24M18-300M3L IS61QDB22M36-250M3 IS61QDB22M36-250M3L IS61QDB24M18-250M3 IS61QDB24M18-250M3L IS61QDB22M36-200M3L IS61QDB24M18-200M3L IS61QDB22M36 D0-35 IS61QDB24M18	PDF
IS61DDB21M36 Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late	Original	oDDB22M18-250M3L 1Mx36 2Mx18 IS61DDB21M36 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI	PDF
D0-35 Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3 Text: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.	Original	IS61QDB42M36-300M3 IS61QDB44M18-300M3 IS61QDB42M36-250M3 IS61QDB44M18-250M3 2Mx36 4Mx18 D0-35 IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3	PDF
IS61QDB41M36 Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18 Text: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.	Original	IS61QDB41M36-250M3 IS61QDB41M36-250M3L IS61QDB41M36-200M3 IS61QDB42M18-200M3 1Mx36 2Mx18 IS61QDB41M36 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18	PDF
Untitled Abstract: No abstract text available Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation	Original	MT54V512H18E 512Kx18) MT54V512H18E	PDF
Untitled Abstract: No abstract text available Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE	Original	MT54V512H18A 165-Pin MT54V512H18A	PDF
Untitled Abstract: No abstract text available Text: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid	Original	IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz	PDF
Untitled Abstract: No abstract text available Text: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid	Original	IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 512Kx36 1Mx18 400MHz 333MHz 300MHz	PDF
Untitled Abstract: No abstract text available Text: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid	Original	IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 1Mx18 IS61QDB451236A 15x17x1	PDF
Untitled Abstract: No abstract text available Text: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid	Original	IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 1Mx18 400MHz 333MHz 300MHz	PDF
Untitled Abstract: No abstract text available Text: IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 4 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available.	Original	IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 4Mx18 13x15	PDF
Untitled Abstract: No abstract text available Text: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     512Kx36 and 1Mx18 configuration available.	Original	IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 512Kx36 1Mx18 13x15	PDF
Untitled Abstract: No abstract text available Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE	Original	MT54V512H18A	PDF
BW35 Abstract: No abstract text available Text: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 36Mb DDRII CIO SRAM 4-WORD BURST MT57W4MH8J MT57W4MH9J MT57W2MH18J MT57W1MH36J FEATURES • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA	Original	MT57W1MH36J BW35	PDF

Untitled Abstract: No abstract text available Text: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation	Original	512Kx18) MT54V512H18E	PDF
Untitled Abstract: No abstract text available Text: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late	Original	IS61DDB21M36-250M3 IS61DDB22M18-250M3 1Mx36 2Mx18	PDF
Untitled Abstract: No abstract text available Text: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE	Original	MT54V2MH18A	PDF
Untitled Abstract: No abstract text available Text: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, Pipelined DDRb2 SRAM 36Mb DDR SRAM 2-Word Burst MT57V2MH18A MT57V1MH36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation	Original	MT57V2MH18A	PDF
Untitled Abstract: No abstract text available Text: 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDRIIb2 SRAM 18Mb DDRII CIO SRAM 2-Word Burst MT57W2MH8B MT57W1MH18B MT57W512H36B FEATURES • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement Pipelined, double-data rate operation	Original		PDF
D018 Abstract: D019 D032 Text: TOSHIBA THMY51E10C70,75,80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY51E10C is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59SM804CFT DRAMs and PLL/Registers on a printed circuit board.	OCR Scan	THMY51E10C70 THMY51E10C70, THMY51E10C75, THMY51E10C80 864-word 72-bit TC59SM804CFT D018 D019 D032	PDF
D018 Abstract: D019 D032 D051 THMY51E10B70 Text: T O S H IB A THMY51E10B70,75,80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY51E10B is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59SM804BFT DRAMs and PLL/Registers on a printed circuit board.	OCR Scan	THMY51E10B70 864-WORD 72-BIT THMY51E10B TC59SM804BFT 72-bit aY51E10B70 D018 D019 D032 D051	PDF
Untitled Abstract: No abstract text available Text: T O S H IB A THMY25E10A70,75,80 TENTATIVE T O S H IB A H Y B R ID D IG ITA L IN T EG R A T ED C IRCUIT 33,554,432-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY25E10A is a 33,554,432-word by 72-bit synchronous dynamic RAM module consisting of	OCR Scan	THMY25E10A70 THMY25E10A 432-word 72-bit TC59SM704AFT 72-bit THMY25E10A)	PDF
OQ45 Abstract: D018 D019 D032 Text: TOSHIBA THMY7216D0CEG-75,-80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216D0CEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6404CFT DRAMs and PLL/Registers on a printed circuit board.	OCR Scan	Y7216D0CEG-75 216-WORD 72-BIT THMY7216D0CEG TC59S6404CFT 168-pin PC133 PC100 OQ45 D018 D019 D032	PDF
ra2b Abstract: No abstract text available Text: TOSHIBA THMY7264E0LEG-75,-80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7264E0LEG is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 36 TC59SM704FT DRAMs and PLL/Registers on a printed circuit board.	OCR Scan	864-WORD 72-BIT THMY7264E0LEG-75 THMY7264E0LEG TC59SM704FT 72-bit THMY7264E0LEG) ra2b	PDF

Privacy Settings

D917 Search Results

D917 Price and Stock

Analog Devices Inc AD9172BBPZ

Analog Devices Inc AD9174BBPZ

Panduit Corp CD9-17B

Analog Devices Inc AD9171BBPZ

Analog Devices Inc AD9177BBPZ

D917 Datasheets Context Search

IS61QDB22M36

IS61DDB21M36

D0-35

IS61QDB41M36

Untitled

Untitled

Untitled

Untitled

Untitled

Untitled

Untitled

Untitled

Untitled

BW35

Untitled

Untitled

Untitled

Untitled

Untitled

D018

D018

Untitled

OQ45

ra2b