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    D295 Price and Stock

    Rochester Electronics LLC MJD2955TF

    TRANS PNP 60V 10A DPAK
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    DigiKey MJD2955TF Bulk 28,000 1,025
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    Flip Electronics NVD2955T4G

    MOSFET P-CH 60V 12A DPAK
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    onsemi NTD2955T4G

    MOSFET P-CH 60V 12A DPAK
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    DigiKey NTD2955T4G Reel 17,500 2,500
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    NTD2955T4G Cut Tape 2,047 1
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    Mouser Electronics NTD2955T4G 9,280
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    Bristol Electronics NTD2955T4G 93 4
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    NTD2955T4G 40,000
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    ComSIT USA NTD2955T4G 635
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    Karl Kruse GmbH & Co KG NTD2955T4G 62,500
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    Richardson RFPD NTD2955T4G 2,500
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    Avnet Asia NTD2955T4G 35 Weeks 2,500
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    onsemi MJD2955T4G

    TRANS PNP 60V 10A DPAK
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    DigiKey MJD2955T4G Reel 5,000 2,500
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    MJD2955T4G Cut Tape 670 1
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    Mouser Electronics MJD2955T4G 4,109
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    Bristol Electronics MJD2955T4G 1,679
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    Rochester Electronics MJD2955T4G 187,473 1
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    onsemi SVD2955T4G

    MOSFET P-CH 60V 12A DPAK
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    DigiKey SVD2955T4G Reel 2,500 2,500
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    SVD2955T4G Cut Tape 2,463 1
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    Avnet Americas SVD2955T4G Reel 25,000 18 Weeks 2,500
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    Mouser Electronics SVD2955T4G 53,927
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    Bristol Electronics SVD2955T4G 295 6
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    Avnet Asia SVD2955T4G 18 Weeks 2,500
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    New Advantage Corporation SVD2955T4G 15,000 1
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    Find more D295 price and stock on Findchips.com

    D295 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Type PDF
    D2950A Unknown Shortform IC and Component Datasheets (Plus Cross Reference Data) Short Form PDF
    D295-4C Klein Tools Tools - Wire Cutters - CUTTER SIDE TAPERED FLUSH 4.25" Original PDF

    D295 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    sab audio

    Abstract: No abstract text available
    Text: 74ACT11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCAS061A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • DW PACKAGE TOP VIEW Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes


    Original     		PDF 74ACT11646 SCAS061A D2957, 500-mA sab audio

    54ACT11521

    Abstract: 74ACT11521 D2957
    Text: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS SCAS023A – D2957, JULY 1978 – REVISED APRIL 1993 • • • • • • • Compares Two 8-Bit Words Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		PDF 54ACT11521, 74ACT11521 SCAS023A D2957, 500-mA 300-mil 54ACT11521 54ACT11521 74ACT11521 D2957

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11623 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS059A – D2957, JULY 1987 – REVISED APRIL 1993 • • • • • • • DW OR NT PACKAGE TOP VIEW Local Bus-Latch Capability Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes


    Original     		PDF 74ACT11623 SCAS059A D2957, 500-mA 300-mil

    74AC11533

    Abstract: No abstract text available
    Text: 54AC11533, 74AC11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS004 − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE 8-Latches in a Single Package


    Original     		PDF 54AC11533, 74AC11533 54AC11533 74AC11533 SCAS004 D2957, 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11533, 74ACT11533 OCTAL DĆTYPE TRANSPARENT LATCHES WITH 3ĆSTATE OUTPUTS ą SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • • • • Eight Latches in a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading


    Original     		PDF 54ACT11533, 74ACT11533 54ACT11533 74ACT11533 SCAS017A D2957, 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW


    OCR Scan     		PDF 54AC11109, 74AC11109 TI0066-- D2957, 500-mA STD-883C 300-mil 54AC11109 74AC11109

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		PDF 54AC11021 74AC11021 D2957. 500-mA 300-mll

    Untitled

    Abstract: No abstract text available
    Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise


    OCR Scan     		PDF 54AC11002, 74AC11002 D2957, 500-mA 300-mil 54AC11002

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible


    OCR Scan     		PDF 54ACT11521, 74ACT11521 D2957, 54ACT11521 74ACT11521 500-mA

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		PDF 54ACT11002 74ACT11002 SCAS003A D2957, 500-mA 300-mll

    1sv 134

    Abstract: No abstract text available
    Text: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS027A - D2957, JULY 1987 - REVISED APRIL 1993 54ACT11640. . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE TOP VIEW B idirectional Bus Transceivers In H ig h-D ensity 24-P in Packages


    OCR Scan     		PDF 54ACT11640, 74ACT11640 SCAS027A D2957, 500-m 300-m 54ACT11640. 74ACT11640 1sv 134

    D2957

    Abstract: No abstract text available
    Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		PDF 500-mA 300-mll AC11240 AC11244, D2957

    74AC11520

    Abstract: No abstract text available
    Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations


    OCR Scan     		PDF 54AC11520 74AC11520 D2957, 500-mA 300-mil 54AC11520 74AC11S20.

    tl401

    Abstract: No abstract text available
    Text: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible


    OCR Scan     		PDF 54ACT11074, 74ACT11074 SCAS046 D2957. 500-mA 300-mil tl401

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer


    OCR Scan     		PDF 54ACT11241, 74ACT11241 I0073-- D2957 500-mA 300-mil

    74AC11533

    Abstract: 123D20
    Text: *»4AP11*511 744011*511 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0085— D2957, JULY 1987— REVISED JAN U AR Y 1990 54AC11533 . . . JT PACKAGE 74AC11533 . . . DW OR NT PACKAGE • 8-Latches in a Single Package • 3-State Bus-Driving Inverting Outputs


    OCR Scan     		PDF 4AP11 TI0085-- D2957, 500-mA 300-mil 54AC11533 74AC11533 74AC11533 123D20

    TI009

    Abstract: No abstract text available
    Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		PDF 54AC11643, I0095-- D2957, 500-mA 300-mil 54AC11643 74AC11643 TI009

    D2957

    Abstract: 1987-REVISEDAPRIL
    Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted


    OCR Scan     		PDF 54ACT11030 74ACT11030 D2957. 1987-REVISEDAPRIL 500-mA 300-mll D2957, D2957

    ti0041

    Abstract: No abstract text available
    Text: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB


    OCR Scan     		PDF 54ACT11000, 74ACT11000 I0041-- D2957, 500-mA 300-mil ti0041

    Untitled

    Abstract: No abstract text available
    Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout


    OCR Scan     		PDF 54AC11074 74AC11074 D2957, 500-mA 300-mil

    sc filter ic mf10

    Abstract: TLC20CN MF10C xq200
    Text: TLC10/MF10A, TLC20/MF1 OC UNIVERSAL DUAL SWITCHED CAPACITOR FILTER D2952, AUGUST 1 9 8 6 -R E V IS E D NOVEMBER 1988 Maximum Clock to Center-Frequency Ratio Error TLC10 . . i ± 0.6% TLC20 . . . ± 1.5% N DUAL-IN-LINE PA CKAG E TO P VIEW I 1LP □ 1 L J 2 0 ] 2 L P


    OCR Scan     		PDF TLC10/MF10A, TLC20/MF1 D2952, TLC10 TLC20 LTC1060 10/MF TLC20/MF10C sc filter ic mf10 TLC20CN MF10C xq200

    Untitled

    Abstract: No abstract text available
    Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		PDF 54AC11020 74AC11020 D2957, 1987-REVISEDAPRIL1993 500-mA 300-mil

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process


    OCR Scan     		PDF 54AC11030, 74AC11030 D2957. 1987-R 500-mA 300-mll S4AC11032-85 54AC11030 D2957,