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Catalog Datasheet	MFG & Type	PDF	Document Tags
CY7C1515JV18-167BZI Abstract: No abstract text available Text: CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1511JV18 – 8M x 8 ■ 300 MHz clock for high bandwidth	Original	PDF	CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit CY7C1511JV18 CY7C1526JV18 CY7C1513JV18 CY7C1515JV18-167BZI
CY7C1515JV18 Abstract: No abstract text available Text: CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■	Original	PDF	CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit CY7C1511JV18 CY7C1513JV18 CY7C1515JV18
CY7C1515JV18 Abstract: No abstract text available Text: CY7C1513JV18 CY7C1515JV18 72-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1513JV18 – 4M x 18 ■ 300 MHz clock for High Bandwidth ■ 4-word Burst for reducing Address Bus Frequency	Original	PDF	CY7C1513JV18 CY7C1515JV18 72-Mbit CY7C1515JV18
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-12560 Spec Title: CY7C1513JV18/CY7C1515JV18, 72-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Anuj Chakrapani (AJU) Replaced by: None CY7C1513JV18 CY7C1515JV18 72-Mbit QDR II SRAM 4-Word Burst Architecture	Original	PDF	CY7C1513JV18/CY7C1515JV18, 72-MBIT CY7C1513JV18 CY7C1515JV18 72-Mbit