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    CY7C1460V33

    Abstract: CY7C1462V33
    Text: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V33 CY7C1462V33 CY7C1464V33 36/2M 18/512K oCY7C1460V33 CY7C1460V33/CY7C1462V33/CY7C1464V33 CY7C1460V33 CY7C1462V33

    BC165

    Abstract: CY7C1460V33 CY7C1462V33 CY7C1462
    Text: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 300, 250, 200, and 167 MHz • Fast access time: 2.3, 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V33 CY7C1462V33 CY7C1464V33 36/2M 18/512K CY7C1460V33/CY7C1462V33/CY7C1464V33 BC165 CY7C1460V33 CY7C1462V33 CY7C1462

    CY7C1460V33

    Abstract: CY7C1462V33
    Text: CY7C1460V33 CY7C1462V33 CY7C1464V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 250, 200, and 167 MHz • Fast access time: 2.7, 3.0 and 3.5 ns


    Original     		PDF CY7C1460V33 CY7C1462V33 CY7C1464V33 36/2M 18/512K CY7C1460V33/CY7C1462V33/CY7C1464V33 CY7C1460V33 CY7C1462V33

    T1X15

    Abstract: CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B CYS25G0101DX OIF-SPI3-01 TRS-X

    CY7C9538

    Abstract: CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c CY7C9538 CYS25G0101DX cypress 1994 sram zero concatenated and OC-3 and STM-1 3C6V 1xVC4-16c T1X15

    CY7C9536B-BLC

    Abstract: CY7C9536B CYS25G0101DX RXD13
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps CY7C9536B-BLC CY7C9536B CYS25G0101DX RXD13

    nobl sram 1994

    Abstract: CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps nobl sram 1994 CY7C9536B-BLC CY7C9536B CYS25G0101DX VC45V

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original     		PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC

    T1X15

    Abstract: CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX
    Text: CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] • Complies with Bellcore GR253 rev.1, 1997


    Original     		PDF CY7C9536B OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xOC-3 4xOC-12 OC-48 50-Mbps T1X15 CY7C9536B-BLC cfk logic chip CY7C9536B CYS25G0101DX

    SDH 209

    Abstract: 1xVC4-16c CY7C9538 CYS25G0101DX VC45V
    Text: CONFIDENTIAL CY7C9538 OC-48/STM-16 Framer with Reconfigurable VC–POSIC2GVC-R Features • OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated • Programmable frame tagging engine for packet preclassification enables such features as


    Original     		PDF CY7C9538 OC-48/STM-16 OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, 707/Y GR253 16xSTS-3c, 4xSTS-12c, 2xSTS-24c, 1xOC-48c SDH 209 1xVC4-16c CY7C9538 CYS25G0101DX VC45V