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    CY7C1413AV18 Search Results

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    CY7C1413AV18 Price and Stock

    Infineon Technologies AG CY7C1413AV18-200BZI

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1413AV18-200BZI Tray
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    Rochester Electronics LLC CY7C1413AV18-200BZI

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1413AV18-200BZI Tray 7
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    Rochester Electronics LLC CY7C1413AV18-250BZC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1413AV18-250BZC Tray 7
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    Infineon Technologies AG CY7C1413AV18-250BZC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1413AV18-250BZC Tray
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    Verical CY7C1413AV18-250BZC 93 7
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    CY7C1413AV18-250BZC 87 7
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    CY7C1413AV18-250BZC 76 7
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    • 100 $53.1875
    • 1000 $48.1
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    Rochester Electronics LLC CY7C1413AV18-200BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1413AV18-200BZC Tray 7
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    CY7C1413AV18 Datasheets (8)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1413AV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413AV18-167BZXC Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413AV18-200BZC Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413AV18-200BZI Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1413AV18-250BZC Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1413AV18-250BZCT Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1413AV18-250BZXC Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1413AV18-278BZC Cypress Semiconductor 36-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF

    CY7C1413AV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    78 ball fbga thermal resistance

    Abstract: No abstract text available
    Text: CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz CY7C1426AV18 78 ball fbga thermal resistance

    HD 46802

    Abstract: CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit HD 46802 CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18

    CY7C1411AV18

    Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz

    CY7C1411AV18

    Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18

    CY7C1411AV18

    Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz b1426AV18 278-MHz CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18

    CY7C1411AV18

    Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 250-MHz CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 CY7C1426AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    PDF CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit CY7C1426AV18, CY7C1415AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit CY7C1426AV18, CY7C1415AV18

    CY7C1411AV18

    Abstract: CY7C1413AV18 CY7C1415AV18 CY7C1426AV18
    Text: CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    PDF CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz CY7C1426AV18 278-MHz CY7C1411AV18 CY7C1413AV18 CY7C1415AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    PDF CY7C1411AV18, CY7C1426AV18 CY7C1413AV18, CY7C1415AV18 36-Mbit CY7C1426AV18, CY7C1415AV18

    AG29

    Abstract: ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22
    Text: ispLever CORE TM QDRII+ SRAM Controller MACO Core User’s Guide June 2008 ipug45_01.5 QDRII+ SRAM Controller MACO Core User’s Guide Lattice Semiconductor Introduction Lattice’s QDRII and QDRII+ QDRII/II+ SRAM Controller MACO core assists the FPGA designer’s efforts by


    Original
    PDF ipug45 AG29 ipug45_01.5 transistor w1d transistor w4B SRAM SAMSUNG FC1152 3ah22

    DB3 C432

    Abstract: 2n2222 sot23 PR55D C458 DB3 C418 db3 c248 BOURNS-3224W-10K transistor C458 transistor c331 DB3 C327
    Text: LatticeSC PCI Express x1 Evaluation Board User’s Guide November 2008 Revision: EB24_01.4 LatticeSC PCI Express x1 Evaluation Board User’s Guide Lattice Semiconductor Introduction This user’s guide describes the LatticeSC PCI Express x1 Evaluation Board featuring the LatticeSC LFSCM3GA25


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    PDF LFSCM3GA25 DB3 C432 2n2222 sot23 PR55D C458 DB3 C418 db3 c248 BOURNS-3224W-10K transistor C458 transistor c331 DB3 C327

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original
    PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC