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    Untitled

    Abstract: No abstract text available
    Text: CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit Density 1M x 18, 512K x 36 ■ 300 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces


    Original     		PDF CY7C1393CV18 CY7C1394CV18 18-Mbit

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original     		PDF CY7C1392CV18, CY7C1992CV18 CY7C1393CV18, CY7C1394CV18 18-Mbit

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-07162 Spec Title: CY7C1393CV18, CY7C1394CV18 18-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: NONE CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture


    Original     		PDF CY7C1393CV18, CY7C1394CV18 18-MBIT CY7C1393CV18 CY7C1394CV18