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    CY7C1355 Price and Stock

    Infineon Technologies AG CY7C1355B-100AC

    IC SRAM 9MBIT PAR 100TQFP
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    DigiKey CY7C1355B-100AC Bag 144
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    • 1000 $12.69215
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    Infineon Technologies AG CY7C1355B-117AC

    IC SRAM 9MBIT PAR 117MHZ 100TQFP
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1355B-117AC Bag 144
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    Infineon Technologies AG CY7C1355C-133BGC

    IC SRAM 9MBIT PARALLEL 119PBGA
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    Infineon Technologies AG CY7C1355C-133AXC

    IC SRAM 9MBIT PARALLEL 100TQFP
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    DigiKey CY7C1355C-133AXC Tray 144
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    • 1000 $11.26701
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    Rochester Electronics CY7C1355C-133AXC 576 1
    • 1 $10.4
    • 10 $10.4
    • 100 $9.78
    • 1000 $8.84
    • 10000 $8.84
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    Infineon Technologies AG CY7C1355C-100AXC

    IC SRAM 9MBIT PAR 100TQFP
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    Find more CY7C1355 price and stock on Findchips.com

    CY7C1355 Datasheets (47)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C135-55JC Cypress Semiconductor 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Original PDF
    CY7C135-55JC Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Original PDF
    CY7C135-55JC Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Original PDF
    CY7C135-55JC Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Scan PDF
    CY7C135-55JI Cypress Semiconductor 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Original PDF
    CY7C135-55JI Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Original PDF
    CY7C135-55JI Cypress Semiconductor 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Scan PDF
    CY7C1355A Cypress Semiconductor 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Original PDF
    CY7C1355A-133AC Cypress Semiconductor 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Original PDF
    CY7C1355B Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-100AC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 9MBIT 100MHZ 100LQFP Original PDF
    CY7C1355B-100AC Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-100AI Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-100BG Cypress Semiconductor Original PDF
    CY7C1355B-100BGC Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-100BZC Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-100BZI Cypress Semiconductor Original PDF
    CY7C1355B-117AC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 9MBIT 117MHZ 100LQFP Original PDF
    CY7C1355B-117AC Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1355B-117AI Cypress Semiconductor 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture Original PDF

    CY7C1355 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C CY7C1355C/CY7C1357C CY7C1355C PDF

    CY7C1357A

    Abstract: GVT71512ZB18
    Text: 1CY7C1357A PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns


    Original     		1CY7C1357A CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 CY7C1357A GVT71512ZB18 PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Functional Description Features • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C 133-MHz CY7C1355C PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355C CY7C1357C 36/512K 133-MHz 100-MHz 100-Pin PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1355B CY7C1357B 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355B CY7C1357B 36/512K 133-MHz 117-MHz 100-MHz CY7C1355B/CY7C1357B 165-ball PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C CY7C1355C/CY7C1357C CY7C1355C PDF

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns


    Original     		CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355C CY7C1357C 36/512K 133-MHz 100-MHz 100-Pin PDF

    CY7C1355C

    Abstract: CY7C1357C
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C 133-MHz CY7C1355C/CY7C1357C CY7C1355C CY7C1357C PDF

    CY7C1355C

    Abstract: CY7C1357C
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C 133-MHz CY7C1355C CY7C1357C PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1355B CY7C1357B PRELIMINARY 256Kx36/512Kx18 Flow-Through SRAM with NoBL Architecture Features • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Pin-for-pin compatible with ZBT Architecture • Fast access times: 6.5 ns, 7.5 ns, and 8.5 ns


    Original     		CY7C1355B CY7C1357B 256Kx36/512Kx18 133-MHz 117-MHz 100-MHz CY7C1355B/CY7C1357B0 PDF

    CY7C1357A-100AC

    Abstract: CY7C1355A CY7C1357A
    Text: CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz


    Original     		CY7C1357A CY7C1355A 36/512K CY7C1355A/CY7C1357A 1357A1 1355A1 CY7C1357A-100AC CY7C1355A CY7C1357A PDF

    CY7C1355A

    Abstract: CY7C1357A
    Text: CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz


    Original     		CY7C1357A CY7C1355A 36/512K CY7C1355A/CY7C1357A 1357A1 1355A1 CY7C1355A CY7C1357A PDF

    CY7C1355C-100BGXI

    Abstract: CY7C1355C CY7C1357C
    Text: CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355C CY7C1357C 36/512K 133-MHz CY7C1355C-100BGXI CY7C1355C CY7C1357C PDF

    CY7C1355V25-133AC

    Abstract: CY7C1355V25 CY7C1357 CY7C1357V25
    Text: 5 CY7C1355V25 CY7C1357V25 PRELIMINARY 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1355V25 CY7C1357V25 256Kx36/512Kx18 133-MHz 117-MHz 100-MHz 80-MHz CY7C1355V25-133AC CY7C1355V25 CY7C1357 CY7C1357V25 PDF

    CY7C1355C

    Abstract: CY7C1357C
    Text: CY7C1355C CY7C1357C PRELIMINARY 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355C CY7C1357C 36/512K 133-MHz CY7C1355C/CY7C1357C CY7C1355C CY7C1357C PDF

    CY7C1355C

    Abstract: No abstract text available
    Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead


    Original     		CY7C1355C, CY7C1357C CY7C1355C/CY7C1357C CY7C1355C PDF

    CY7C1355V25

    Abstract: CY7C1357 CY7C1357V25
    Text: 5 CY7C1355V25 CY7C1357V25 PRELIMINARY 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1355V25 CY7C1357V25 256Kx36/512Kx18 133-MHz 117-MHz CY7C1355V25 CY7C1357 CY7C1357V25 PDF

    CY7C1355B

    Abstract: CY7C1357B 63a3
    Text: CY7C1355B CY7C1357B 9-Mb 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Features • JTAG boundary scan for BGA and fBGA packages • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355B CY7C1357B 36/512K 133-MHz 117-MHz 100-MHz CY7C1355B/CY7C1357B CY7C1355B CY7C1357B 63a3 PDF

    CY7C1355A

    Abstract: CY7C1357A GVT71512ZB18
    Text: CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture Features inputs include all addresses, all data inputs, depth-expansion Chip Enables CE, CE2, and CE3 , Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,


    Original     		CY7C1357A CY7C1355A 36/512K CY7C1355A/GVT71256ZB36 CY7C1355A/CY7C1357A CY7C1355A CY7C1357A GVT71512ZB18 PDF

    CY7C1355B

    Abstract: CY7C1357B 75-bit-long 38T5
    Text: CY7C1355B CY7C1357B 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero


    Original     		CY7C1355B CY7C1357B 36/512K 133-MHz CY7C1355B/CY7C1357B design57B 165-ball CY7C1355B CY7C1357B 75-bit-long 38T5 PDF

    CY7C1355V25

    Abstract: CY7C1357 CY7C1357V25
    Text: 5 CY7C1355V25 CY7C1357V25 PRELIMINARY 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    Original     		CY7C1355V25 CY7C1357V25 256Kx36/512Kx18 133-MHz 117-MHz 100-MHz 80-MHz CY7C1355V25 CY7C1357 CY7C1357V25 PDF

    CY7C1355B

    Abstract: CY7C1357 CY7C1357B nobl sram
    Text: CY7C1355B CY7C1357B PRELIMINARY 256Kx36/512Kx18 Flow-Through SRAM with NoBL Architecture Features • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Pin-for-pin compatible with ZBT Architecture • Fast access times: 6.5 ns, 7.5 ns, and 8.5 ns


    Original     		CY7C1355B CY7C1357B 256Kx36/512Kx18 133-MHz 117-MHz 100-MHz CY7C1355B/CY7C1357B CY7C1355B CY7C1357 CY7C1357B nobl sram PDF

    CY7C1355V25

    Abstract: CY7C1357 CY7C1357V25
    Text: CY7C1355V25 CY7C1357V25 PRELIMINARY y CYPRESS 256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture Features • Pin compatible and functionally equivalent to ZBT™ de­ vices • Supports 133-MHz bus operations with zero wait states — Data is transferred on every clock


    OCR Scan     		CY7C1355V25 CY7C1357V25 256Kx36/512Kx18 133-MHz 117-MHz 100-MHz 80-MHz CY7C1355V25 CY7C1357 CY7C1357V25 PDF