Untitled
Abstract: No abstract text available
Text: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8
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Original
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CY7C1317KV18,
CY7C1917KV18
CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1317KV18
CY7C1917KV18
CY7C1319KV18
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18 Mbit density 2 M x 8, 2 M × 9, 1 M × 18, 512 K × 36 CY7C1317KV18 – 2 M × 8
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Original
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CY7C1317KV18,
CY7C1917KV18
CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1317KV18
CY7C1917KV18
CY7C1319KV18
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1317KV18, CY7C1917KV18 CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Functional Description • 18 Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 ■ 333-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency
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Original
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CY7C1317KV18,
CY7C1917KV18
CY7C1319KV18,
CY7C1321KV18
18-Mbit
333-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth
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Original
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CY7C1319KV18/CY7C1321KV18
18-Mbit
CY7C1319KV18
333-MHz
CY7C1321KV18
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth
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Original
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CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1319KV18
333-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth
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Original
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CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1319KV18
333-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth
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Original
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CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1319KV18
333-MHz
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PDF
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M30-15
Abstract: No abstract text available
Text: CY7C1319KV18, CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth
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Original
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CY7C1319KV18,
CY7C1321KV18
18-Mbit
CY7C1319KV18
333-MHz
M30-15
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PDF
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