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    CY7C1313AV18 Search Results

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    CY7C1313AV18 Price and Stock

    Rochester Electronics LLC CY7C1313AV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1313AV18-200BZC Bulk 780 16
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    Rochester Electronics LLC CY7C1313AV18-167BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1313AV18-167BZC Bulk 16
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    Infineon Technologies AG CY7C1313AV18-167BZC

    1MX18 1.8V QDR-II SRAM (4-WORD BURST) - Trays (Alt: CY7C1313AV18-167BZ)
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    Avnet Americas CY7C1313AV18-167BZC Tray 4 Weeks 19
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    Infineon Technologies AG CY7C1313AV18-200BZC

    1MX18 1.8V QDR-II SRAM (4-WORD BURST) - Trays (Alt: CY7C1313AV18-200BZ)
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Avnet Americas CY7C1313AV18-200BZC Tray 4 Weeks 19
    • 1 $20.15
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    Cypress Semiconductor CY7C1313AV18-200BZC

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    Bristol Electronics CY7C1313AV18-200BZC 126
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    Rochester Electronics CY7C1313AV18-200BZC 780 1
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    CY7C1313AV18 Datasheets (5)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C1313AV18 Cypress Semiconductor 18-Mb QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313AV18-167BZC Cypress Semiconductor 18-Mb QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313AV18-200BZC Cypress Semiconductor 18-Mb QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313AV18-250BZC Cypress Semiconductor 18-Mb QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313AV18-250BZXC Cypress Semiconductor 18-Mb QDR -II SRAM 4-Word Burst Architecture Original PDF

    CY7C1313AV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1311AV18

    Abstract: CY7C1313AV18 CY7C1315AV18
    Text: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original     		PDF CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb 250-MHz CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 CY7C1311AV18 CY7C1313AV18 CY7C1315AV18

    CY7C1311AV18

    Abstract: CY7C1313AV18 CY7C1315AV18
    Text: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original     		PDF CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb 250-MHz CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 CY7C1311AV18 CY7C1313AV18 CY7C1315AV18

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original     		PDF CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC

    EP2S60

    Abstract: No abstract text available
    Text: Interfacing QDRTM-II SRAM with StratixTM, Stratix II and Stratix GX Devices AN4064 Introduction Synchronous static RAM SRAM architectures are evolving to support the highthroughput requirements of communications, networking, and digital signal processing (DSP) systems. The successor to Quad Data Rate (QDR™) SRAM,


    Original     		PDF AN4064 EP2S60

    CY7C1313AV18-250BZC

    Abstract: EP1S60 EP2S60F1020C5ES F1020 v32-88
    Text: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices Application Note 326 May 2008, ver. 5.1 Introduction Synchronous static RAM SRAM architectures support the high throughput requirements of communications, networking, and digital


    Original     		PDF