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    CY7C1298H Search Results

    CY7C1298H Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C1298H Cypress Semiconductor 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1298H-100AXC Cypress Semiconductor 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1298H-100AXI Cypress Semiconductor 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1298H-133AXC Cypress Semiconductor 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Original PDF

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    CY7C1298H

    Abstract: CY7C1298H-100AXC
    Text: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		PDF CY7C1298H 18-bit 166-MHz 100-Pin CY7C1298H CY7C1298H-100AXC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		PDF CY7C1298H 18-bit 166-MHz 100-Pin

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		PDF CY7C1298H 18-bit 166-MHz 133-MHz 100-pin CY7C1298H

    Untitled

    Abstract: No abstract text available
    Text: PRELIMINARY CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		PDF CY7C1298H 18-bit 166-MHz 133-MHz 100-pin CY7C1298H