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    CY7C1231H Search Results

    CY7C1231H Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Type PDF
    CY7C1231H Cypress Semiconductor 2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1231H-133AXC Cypress Semiconductor 2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture Original PDF
    CY7C1231H-133AXI Cypress Semiconductor 2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture Original PDF

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    CY7C1231H

    Abstract: CY7C1231H-133AXI
    Text: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1231H 133-MHz CY7C1231H w28408 CY7C1231H-133AXI

    Untitled

    Abstract: No abstract text available
    Text: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1231H 133-MHz 100-pin

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-00207 Spec Title: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Sunset Owner: Jayasree Nayar (njy) Replaced by: None CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture Features


    Original     		PDF CY7C1231H CY7C1231H 133-MHz

    CY7C1231H

    Abstract: CY7C1231H-133AXI
    Text: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1231H 133-MHz CY7C1231H CY7C1231H-133AXI

    Untitled

    Abstract: No abstract text available
    Text: CY7C1231H PRELIMINARY 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™


    Original     		PDF CY7C1231H 133-MHz 100-MHz 100-lead CY7C1231H