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    CY7C1223H Search Results

    CY7C1223H Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1223H Cypress Semiconductor 2-Mbit (128K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1223H-133AXC Cypress Semiconductor 2-Mbit (128K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1223H-166AXC Cypress Semiconductor 2-Mbit (128K x 18) Pipelined DCD Sync SRAM Original PDF
    CY7C1223H-166AXI Cypress Semiconductor 2-Mbit (128K x 18) Pipelined DCD Sync SRAM Original PDF

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    CY7C1223H

    Abstract: No abstract text available
    Text: CY7C1223H 2-Mbit 128K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K x 18-bit common I/O architecture


    Original     		PDF CY7C1223H 18-bit 166-MHz 133-MHz 100-pin CY7C1223H

    Untitled

    Abstract: No abstract text available
    Text: CY7C1223H PRELIMINARY 2-Mbit 128K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K x 18-bit common I/O architecture


    Original     		PDF CY7C1223H 18-bit 166-MHz 133-MHz 100-pin CY7C1223H

    CY7C1223H

    Abstract: No abstract text available
    Text: CY7C1223H 2-Mbit 128K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K x 18-bit common I/O architecture


    Original     		PDF CY7C1223H 18-bit 166-MHz 133-MHz 100-pin CY7C1223H

    Untitled

    Abstract: No abstract text available
    Text: CY7C1223H PRELIMINARY 2-Mbit 128K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 128K x 18-bit common I/O architecture


    Original     		PDF CY7C1223H 18-bit 166-MHz 133-MHz 100-pin CY7C1223H