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Catalog Datasheet	MFG & Type	PDF	Document Tags
3M Touch Systems Abstract: No abstract text available Text: CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.0 cycles: ■	Original	PDF	CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit 450-MHz CY7C1146KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency Configurations Features • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.0 cycles: ■	Original	PDF	CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit 450-MHz CY7C1146KV18
Untitled Abstract: No abstract text available Text: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:	Original	PDF	CY7C1148KV18/CY7C1150KV18 18-Mbit 450-MHz CY7C1148KV18 CY7C1150KV18
2894043 Abstract: 3M Touch Systems Text: CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:	Original	PDF	CY7C1148KV18, CY7C1150KV18 18-Mbit CY7C1148KV18 450-MHz 2894043 3M Touch Systems