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    CY7C1150KV18 Search Results

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    CY7C1150KV18 Price and Stock

    Rochester Electronics LLC CY7C1150KV18-450BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1150KV18-450BZC Tray 568 9
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    Rochester Electronics LLC CY7C1150KV18-400BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1150KV18-400BZXC Tray 419 9
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    Rochester Electronics LLC CY7C1150KV18-400BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1150KV18-400BZC Tray 338 9
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    Rochester Electronics LLC CY7C1150KV18-400BZXI

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1150KV18-400BZXI Bulk 235 9
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    • 10 $37.14
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    Infineon Technologies AG CY7C1150KV18-400BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1150KV18-400BZC Tray
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    CY7C1150KV18 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1150KV18-400BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA Original PDF
    CY7C1150KV18-400BZXC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA Original PDF
    CY7C1150KV18-400BZXI Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA Original PDF
    CY7C1150KV18-450BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 450MHZ 165FBGA Original PDF

    CY7C1150KV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:


    Original
    PDF CY7C1148KV18/CY7C1150KV18 18-Mbit 450-MHz CY7C1148KV18 CY7C1150KV18

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.0 cycles: ■


    Original
    PDF CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit 450-MHz CY7C1146KV18 3M Touch Systems

    Untitled

    Abstract: No abstract text available
    Text: CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency Configurations Features • 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36) With Read Cycle Latency of 2.0 cycles: ■


    Original
    PDF CY7C1146KV18, CY7C1157KV18 CY7C1148KV18, CY7C1150KV18 18-Mbit 450-MHz CY7C1146KV18

    2894043

    Abstract: 3M Touch Systems
    Text: CY7C1148KV18, CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:


    Original
    PDF CY7C1148KV18, CY7C1150KV18 18-Mbit CY7C1148KV18 450-MHz 2894043 3M Touch Systems