CY7B9910
Abstract: CY7B9920
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines
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CY7B9910
CY7B9920
80-MHz
24-pin
CY7B9910
CY7B9920
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CY7B9910
Abstract: CY7B9920
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows
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CY7B9910
CY7B9920
24-pin
CY7B9910
CY7B9920
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows
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CY7B9910
CY7B9920
24-pin
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs
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CY7B9910
CY7B9920
24-pin
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CY7B9910
Abstract: CY7B9920
Text: CY7B9910 CY7B9920 W ances as low as 50 while delivering miniĆ mal and specified output skews and fullĆ swing logic levels CY7B9910 TTL or CY7B9920 CMOS . Features D All outputs skew <100 ps typical (250 max.) D D D D D D D 15Ć to 80ĆMHz output operation
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CY7B9910
CY7B9920
CY7B9910
CY7B9920
80MHz
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CY7B9910
Abstract: CY7B9920 BUT12
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs
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CY7B9910
CY7B9920
24-pin
CY7B9910
CY7B9920
BUT12
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 PRELIMINARY Low Skew Clock Buffer Features • All outputs skew <100 ps typical 250 max. ■ 15 to 80 MHz output operation ■ Zero input to output delay The completely integrated PLL enables “zero delay” capability. External divide capability, combined with the internal PLL, allows
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CY7B9910
CY7B9920
24-pin
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CY7B9910
Abstract: CY7B9920
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines
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CY7B9910
CY7B9920
24-pin
CY7B9910
CY7B9920
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Clock Buffers
Abstract: FCT Fast CMOS TTL Logic CY7B9910 CY7B9920
Text: PRESS RELEASE CYPRESS INTRODUCES LOW-COST, LOW-SKEW CLOCK BUFFERS "RoboClock Jr." Devices Offer Near Zero Propagation Delay, 250 ps Pin-to-Pin Skew SAN JOSE, Calif., February 20, 1995 - Cypress Semiconductor Corporation today introduced the low-cost, low-skew CY7B9910 and CY7B9920 clock buffers. The two
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CY7B9910
CY7B9920
CY7B9910/20
24-pin
000-unit
Clock Buffers
FCT Fast CMOS TTL Logic
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CY7B991-LMB
Abstract: CY7B9910 CY7B9920 EME-6300H CY7C9910
Text: Qualification Report May, 1995 QTP# 95021 Version 1.0 PROGRAMMABLE SKEWCLOCK BUFFER CY7B9910-SC CY7B9920-SC Programable Skew Clock Buffer Driver TTL Programable Skew Clock Buffer Driver (CMOS) PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:
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CY7B9910-SC
CY7B9920-SC
CY7B9910
CY7B9920
7B991A0/46
CY7B991/CY7B992/CY7B9910/CY7B9920
24-pins
CY7B9910/9920
-4400V
CY7B991-LMB
CY7B9920
EME-6300H
CY7C9910
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CY7B9910
Abstract: CY7B9920
Text: 920 CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines
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CY7B9910
CY7B9920
80-MHz
24-pin
CY7B9910/CY7B9920
CY7B9910
CY7B9920
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Low Skew Clock Buffer Features Block Diagram Description • All outputs skew < 100 ps typical 250 max Phase Frequency Detector and Filter ■ 15 to 80 MHz output operation ■ Zero input to output delay ■ 50% duty cycle outputs
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CY7B9910
CY7B9920
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features Block Diagram Description • All Outputs Skew <100 ps typical 250 max. Phase Frequency Detector and Filter ■ 15 to 80 MHz Output Operation ■ Zero Input to Output Delay ■ 50% Duty Cycle Outputs ■ Outputs drive 50Ω terminated lines
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CY7B9910
CY7B9920
24-pin
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CY7B9910
Abstract: CY7B9920
Text: fax id: 3516 1CY 7B9 92 0 CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs
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CY7B9910
CY7B9920
80-MHz
24-pin
CY7B9910
CY7B9920
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CY7B991
Abstract: CY7B9910 CY7B9911 CY7B992 CY7B9920
Text: fax id: 3613 Using CY7B991 RoboClock , CY7B9911 (RoboClock+) and CY7B9910 (Robo Jr.) in 3.3-Volt Environments Introduction The RoboClock family of low skew clock buffers includes five products listed in Table 1. Table 1. RoboClock Family Cypress Part No.
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CY7B991
CY7B9911
CY7B9910
CY7B992
CY7B9920
CY7B991
CY7B9910
CY7B9911
CY7B992
CY7B9920
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PLD 22V10
Abstract: Time Clock phase latter CY7B991 CY7B9910 CY7B9911 CYB992 SIGNAL PATH DESIGNER
Text: fax id: 3609 Innovative Designs with CY7B991/2 RoboClock , CY7B9911 (RoboClock+) and CY7B9910/20 (Robo Jr.) Clock Buffers Overview This article discusses various applications of the Cypress Phase Locked Loop-based, skew-defeating clock buffers known as RoboClock. It is assumed that the reader has a
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CY7B991/2
CY7B9911
CY7B9910/20
PLD 22V10
Time Clock
phase latter
CY7B991
CY7B9910
CY7B9911
CYB992
SIGNAL PATH DESIGNER
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AN1144
Abstract: AN-1144 CY7B991 CY7B9910 CY7B9911 CY7B991V CYBUS3384 Signal Path Designer
Text: Innovative Designs Using the RoboClock Family AN1144 Author: Kelly Mass Associated Project: No Associated Application Notes: None Application Note Abstract AN1144 discusses various applications of the Cypress PLL-based, skew-defeating clock buffers known as RoboClock®. It is
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AN1144
AN1144
AN-1144
CY7B991
CY7B9910
CY7B9911
CY7B991V
CYBUS3384
Signal Path Designer
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CY7B9910
Abstract: CY7B9920
Text: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay
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15-to
80-MHz
24-pin
CV7B9910
CY7B9920
CY7B9910
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Untitled
Abstract: No abstract text available
Text: fax id: 3516 CY7B9910 CY7B9920 •■mmmmggf ¿mw Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Zero input to output delay
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CY7B9910
CY7B9920
80-MHz
24-pin
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Untitled
Abstract: No abstract text available
Text: fax id: 3516 CY7B9910 CY7B9920 Low Skew Clock Buffer Block Diagram Description Featu res Phase Frequency Detector and Filter • All outputs skew <100 ps typical 250 max. • 1 5 -to 80-MHz output operation These two blocks accept inputs from the reference frequency
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CY7B9910
CY7B9920
80-MHz
24-pin
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 CYPRESS Low Skew Clock Buffer Block Diagram Description Features All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correc
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CY7B9910
CY7B9920
80-MHz
24-pin
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 Low Skew Clock Buffer Features • • • • • • • • • Block Diagram Description All outputs skew <100 ps typical 250 max. 1 5 -to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs O utputs drive 50& term inated lines
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CY7B9910
CY7B9920
80-MHz
24-pin
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Untitled
Abstract: No abstract text available
Text: CY7B9910 CY7B9920 PRELIMINARY CYPRESS Low Skew Clock Buffer Features • All outputs skew <250 ps typical 500 max. • 15- to 80-MHz output operation • Zero input to output delay • 50% duty-cycle outputs • Outputs drive 50Q terminated lines • Low operating current
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CY7B9910
CY7B9920
80-MHz
24-pin
CY7B9910
CY7B9920
24-Lead
CY7B9920â
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CY7B9910
Abstract: CY7B9920
Text: fax id: 3516 ’*“ ££¡388^ CY7B9910 CY7B9920 CYPRESS Low Skew Clock Buffer Block Diagram Description Features • • • • • • • • • Phase Frequency Detector and Filter All outputs skew <100 ps typical 250 max. 15- to 80-MHz output operation
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15-to
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24-pin
CV7B9910
CY7B9920
CY7B99107.
CY7B9910
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