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    CML ECL COMPATIBLE Search Results

    CML ECL COMPATIBLE Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    SF-10GSFPPLCL-000 Amphenol Cables on Demand Amphenol SF-10GSFPPLCL-000 SFP+ Optical Module - 10GBASE-SR (up to 300m/984') SFP+ Multimode Optical Transceiver Module (Duplex LC Connectors) - Cisco & HP Compatible Datasheet

    CML ECL COMPATIBLE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    485G

    Abstract: NB7L32M MARKING 224 QFN-16
    Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Descriptions The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The


    Original     		PDF NB7L32M 14GHz NB7L32M NB7L32M/D 485G MARKING 224 QFN-16

    Untitled

    Abstract: No abstract text available
    Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The


    Original     		PDF NB7L32M 14GHz NB7L32M NB7L32Mâ NB7L32M/D

    Untitled

    Abstract: No abstract text available
    Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The


    Original     		PDF NB7L32M 14GHz NB7L32M/D

    485G

    Abstract: NB7L32M
    Text: NB7L32M 2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal Termination Description The NB7L32M is an integrated ÷2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL Positive ECL , CML, or LVDS. The


    Original     		PDF NB7L32M 14GHz NB7L32M NB7L32M/D 485G

    package marking 504c

    Abstract: ICS853S 853S310CVILF
    Text: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL


    Original     		PDF ICS853S310I ICS853S310I package marking 504c ICS853S 853S310CVILF

    Untitled

    Abstract: No abstract text available
    Text: Low Skew, 1-to-8 Differential-to3.3V LVPECL/ECL Fanout Buffer ICS853S310I DATA SHEET General Description Features The ICS853S310I is a low skew, high performance 1-to-8 Differential-to-3.3V LVPECL/ECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept LVPECL, LVDS, CML and SSTL


    Original     		PDF ICS853S310I ICS853S310I

    CX60077

    Abstract: dense wavelength division multiplexer
    Text: Network Access Division Data Sheet CX60077 2.5 Gbps Long Haul Laser Driver Key Features Applications • • • • • • • • • • Single supply : -5.2 Volts CML interface with capability of receiving ECL level Low power consumption ≤ 400 mW


    Original     		PDF CX60077 OC-48) CX60077 dense wavelength division multiplexer

    PULSE WIDTH MODULATION CONTROL CIRCUIT

    Abstract: No abstract text available
    Text: 19-4803; Rev 0; 4/01 10.7Gbps EAM Driver Features ♦ Single -5.2V Power Supply The MAX3935 accepts differential ECL or ground-referenced CML clock and data-input signals. Inputs are terminated with on-chip 50Ω resistors. An input-data retiming latch can be used to reject input-patterndependent jitter if a clock signal is available.


    Original     		PDF MAX3935 PULSE WIDTH MODULATION CONTROL CIRCUIT

    MAX3910

    Abstract: MAX3935 MAX3935EGJ STM-64
    Text: 19-4803; Rev 0; 4/01 10.7Gbps EAM Driver Features ♦ Single -5.2V Power Supply The MAX3935 accepts differential ECL or ground-referenced CML clock and data-input signals. Inputs are terminated with on-chip 50Ω resistors. An input-data retiming latch can be used to reject input-patterndependent jitter if a clock signal is available.


    Original     		PDF MAX3935 110mA MAX3910 MAX3935EGJ STM-64

    SY87702LHI

    Abstract: No abstract text available
    Text: 3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY FEATURES SY87702L FINAL DESCRIPTION • 3.3V power supply ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48*, and ATM ■ Compatible with FDDI, Gigabit Ethernet, Fibre


    Original     		PDF 28Mbps-2 SY87702L OC-12, OC-48* 28Mbps 64-Pin SY87702L SY87702LHI

    Untitled

    Abstract: No abstract text available
    Text: 3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY FEATURES PRELIMINARY SY87702L DESCRIPTION • 3.3V power supply ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48*, and ATM ■ Compatible with FDDI, Gigabit Ethernet, Fibre


    Original     		PDF 28Mbps-2 SY87702L OC-12, OC-48* 28Mbps 64-Pin OC-48 H64-1 H64-1)

    SY87702L

    Abstract: SY87702LHG SY87702LHI SY87702LHITR SY87721L
    Text: Micrel, Inc. 3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY FEATURES SY87702L SY87702L DESCRIPTION • 3.3V power supply ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48*, and ATM ■ Compatible with FDDI, Gigabit Ethernet, Fibre


    Original     		PDF 28Mbps-2 SY87702L OC-12, OC-48* 28Mbps 64-Pin M9999-072706 SY87702L SY87702LHG SY87702LHI SY87702LHITR SY87721L

    ANSI C39.1

    Abstract: R20 marking SY87702LHITR SY87702L SY87702LHG SY87702LHGTR SY87702LHI SW DIP5 SY87702LH
    Text: Micrel, Inc. 3.3V 28Mbps-2.5Gbps AnyRate CLOCK AND DATA RECOVERY FEATURES SY87702L SY87702L DESCRIPTION • 3.3V power supply ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, OC-48*, and ATM ■ Compatible with FDDI, Gigabit Ethernet, Fibre


    Original     		PDF 28Mbps-2 SY87702L OC-12, OC-48* 28Mbps 64-Pin M9999-102405 ANSI C39.1 R20 marking SY87702LHITR SY87702L SY87702LHG SY87702LHGTR SY87702LHI SW DIP5 SY87702LH

    KSZ8041

    Abstract: LM2576 MTBF vcsel spice model MIC4129 mic44r22 ksz8692 MICREL MIC marking DFB laser diode spice model KSZ9021RLI KSZ8041TLI
    Text: Military Catalog May 2009 Dear Valued Customer, Micrel is an enduring DSCC certified company that has, for many years, provided Mil-Std-883B products in hermetic ceramic packages. We have also provided products governed by source controlled drawings SCD where baseline control is important. Our in-house, U.S.-based wafer


    Original     		PDF Mil-Std-883B M0014-051409 KSZ8041 LM2576 MTBF vcsel spice model MIC4129 mic44r22 ksz8692 MICREL MIC marking DFB laser diode spice model KSZ9021RLI KSZ8041TLI

    ksz8863 EVAL BOARD

    Abstract: KSZ8863 nu-horizons KSZ9021RLI KSZ8041NLI KSZ9021GN transistors sot-223 06a KS8995MA ksz9021rl MIC3201
    Text: Shortform Catalog February 2010 Shortform Catalog February 2010 2010 Micrel, Inc. The information furnished by Micrel, Inc., in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use, nor any infringements of patents


    Original     		PDF 747-NUHO M0009-012910 ksz8863 EVAL BOARD KSZ8863 nu-horizons KSZ9021RLI KSZ8041NLI KSZ9021GN transistors sot-223 06a KS8995MA ksz9021rl MIC3201

    QFN-16

    Abstract: SUBCC qfn16 CML ECL termination NBSG14
    Text: Enabling Energy Efficient Solutions Product Overview Created on: 10/26/2011 NBSG14: 2.5 V / 3.3 V SiGe 1:4 Differential Clock/Data Fanout Buffer with RSECL Outputs For complete documentation, see the data sheet Product Description The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for ultra-low skew and jitter.


    Original     		PDF NBSG14: NBSG14 50-ohm NBSG14MNHTBG NBSG14MNR2G QFN16 QFN16 NBSG14MNG QFN-16 SUBCC CML ECL termination

    SH100E

    Abstract: siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191
    Text: 7 1991 SIEMENS ASIC Product Description SH100E ECL/CML Gale Amy Family FEATURES • Gate complexities from 1,500 to 16,000 gates ■ 120 ps gate delay, 90 ps differential • 1.5 GHz D flip-flop, 1.7 GHz differential ■ Both ECL and CML macro families ■ TTL I/O available


    OCR Scan     		PDF SH100E 10KH/100K M33S001 SH100E siemens SH100E elxr siemens Nand gate SH100E5 TRANSISTOR K 2191

    HM3500

    Abstract: No abstract text available
    Text: HONEYüJELL D I G I T A L P R O D U C T bt De | 4 S S m S 3 □□0DD73 7 | T-42-11-15 MAY 1985 HM3500 ECL/TTL GATE ARRAY PRELIMINARY PRODUCT DESCRIPTION The HM3500 Figure 1 is a 400 picosecond, 3500 equivalent gate density VLSI monolithic integrated circuit using Honeywell’s ADB-II fabrication process.


    OCR Scan     		PDF 0DD73 T-42-11-15 HM3500 10K/KH HM3500

    transistor a473

    Abstract: A473 transistor conhex chip die npn transistor CML ECL compatible
    Text: HONEYWELL "DIGITAL PRODUCT bt. dË | MSS1M5B ODOOOEt. T f' T-42-11-13 MARCH 1985 ECL GATE ARRAY HE2000 PRODUCT DESCRIPTION The HE2000 Gate Array Figure 1 is a 300 picosecond, 2000 equivalent gate density Very Large Scale Integration (VLSI) monolithic integrated circuit built using Honeywell’s


    OCR Scan     		PDF T-42-11-13 HE2000 HE2000 10K/KH transistor a473 A473 transistor conhex chip die npn transistor CML ECL compatible

    A473 transistor

    Abstract: transistor a473 A473 CML termination 50 Ohm external termination volt HE2000
    Text: MARCH 1985 HE2000 ECL GATE ARRAY PRODUCT DESCRIPTION The HE2000 Gate Array Figure 1 is a 300 picosecond, 2000 equivalent gate density Very Large Scale Integration (VLSI) monolithic integrated circuit built using Honeywell’s ADB-II fabrication process. The array is composed of an


    OCR Scan     		PDF HE2000 HE2000 10K/KH A473 transistor transistor a473 A473 CML termination 50 Ohm external termination volt

    64 PIN CERDIP

    Abstract: No abstract text available
    Text: HONEYWELL DIGITAL PRODUCT bb D E * 4SS14S3 0000050 b • ■ ■ RAD HARD ECL/TTL GATE ARRAY PRODUCT DESCRIPTION The HM1000R Gate Array Figure 1 is an 800 pico­ second, 1000 equivalent gate density LSI monolithic integrated circuit built using Honeywell’s radiation


    OCR Scan     		PDF 4SS14S3 T-42-11-15 HM1000R 10K/KH 45S14S3 HM1000R 64-Pin 64 PIN CERDIP

    HP83000

    Abstract: LI-300 Signal Path designer FLIP FLOP toggle
    Text: O V A t f k ln f lf A ll Lig h tn in g Series - LI300, LI1000 m m tM m jrtm . W % S m m Ultrahigh-Speed GaAs Gate Arrays Features Figure 1 Photomicrograph of the Lightning LI300 array • Advanced HBT GaAs process for high performance • Two array sizes: 300 or 1000 equivalent gates


    OCR Scan     		PDF LI300, LI1000 CMO39-90 AA30450 7A11G73 HP83000 LI-300 Signal Path designer FLIP FLOP toggle

    L42n

    Abstract: HM3500 adb 630 L43n "alu 4 bit" ECL IC NAND L44N PT06-16-8P-S/transistor 03e
    Text: H0NEYWE1_I_/SS ELEK-, MIL [13 I>e | 4551872 DD00212 D • “ H o n eyw e ll r - n - ll'O HM3500, hvmioooo, HE12000 Preliminary ADVANCED DIGITAL BIPOLAR GATE ARRAY FAMILY FAMILY FEATURES • Broad Performance Optimized Family Allows Flexible System Partitioning:


    OCR Scan     		PDF DD00212 HM3500, HE12000 ECL10K/KH/100K 148-Pin MIL-M-38510/600 MIL-STD-883C L42n HM3500 adb 630 L43n "alu 4 bit" ECL IC NAND L44N PT06-16-8P-S/transistor 03e

    Untitled

    Abstract: No abstract text available
    Text: H OlM EYüJELL/SS ELEK-, M IL 03 D Ë| 4551Ö72 DDGG3].t □ T -9 2 -//-Û 7 Honeywell Radiation Hardened Bipolar Gate Array Family " Preliminary HM3500R, HVM10000R Family Features • Strategic Radiation Hardness Allows Spaced Based System Operations • Broad Performance Optimized Family Allows Flexible


    OCR Scan     		PDF HM3500R, HVM10000R to172 148-Pin 244-Pin M2010, M2023 M1008,