Untitled
Abstract: No abstract text available
Text: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36
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SN54ACT3641
SGBS309A
5962-9560801QYA
5962-9560801NXD
SCAA013A
SCAA008A
SCLA008
SZZU001B,
SDYU001N,
SCET004,
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IW4042BD
Abstract: IW4042BN
Text: TECHNICAL DATA IW4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS IW4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all
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IW4042B
IW4042B
012AC)
IW4042BD
IW4042BN
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CY7C4255V
Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Text: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to
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CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
8K/16K/32K/64Kx18
CY7C4255/65/75/85V
CY7C42X5V
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
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r2s3
Abstract: CD40192B CD40192BMS CD40193B CD40193BMS
Text: CD40192BMS CD40193BMS CMOS Presettable Up/Down Counters Dual Clock With Reset December 1992 Features Description • CD40192BMS - BCD Type CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines,
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CD40192BMS
CD40193BMS
CD40192BMS
CD40193BMS
r2s3
CD40192B
CD40193B
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C4558
Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)
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CY7C455
CY7C456
CY7C457
52-pin
CY7C455)
CY7C456)
CY7C457)
83-MHz
C4558
C4554
C4557
c455
CY7C455-14JI
CY7C455
CY7C456
CY7C457
CY7C447
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Untitled
Abstract: No abstract text available
Text: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs
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SN54ABT3614
SGBS308F
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Untitled
Abstract: No abstract text available
Text: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 D D D D D Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be Synchronized to Independent System
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SN74ACT7881
SCAS227E
SN74ACT7882,
SN74ACT7884,
SN74ACT7811
50-pF
68-Pin
80-Pin
D17udio
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Untitled
Abstract: No abstract text available
Text: SN74GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and
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SN74GTLPH32912
36-BIT
SCES379A
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Untitled
Abstract: No abstract text available
Text: SN54ABT7819 512 x 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS305D – AUGUST 1994 – REVISED APRIL 1998 D D D D D D D Member of the Texas Instruments Widebus Family Advanced BiCMOS Technology Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
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SN54ABT7819
SGBS305D
50-pF
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Untitled
Abstract: No abstract text available
Text: HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /
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HD74LS165A
REJ03D0449â
LS165A
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Untitled
Abstract: No abstract text available
Text: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags
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SN74ACT7881
SCAS227C
SN74ACT7882,
SN74ACT7884,
SN74ACT7811
50-pF
68-Pin
80-Pln
DO-D17
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CIRCUIT DIAGRAM OF Bf 199
Abstract: No abstract text available
Text: TC4042BP/BF/BFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042B QUAD CLOCKED "D " LATCH_ TC4042B contains fo u r circuits o f "D " type latches having common CLOCK input and POLARITY input. W hen POLARITY input is placed at "H " level, D input appears
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TC4042BP/BF/BFN
TC4042B
CIRCUIT DIAGRAM OF Bf 199
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Untitled
Abstract: No abstract text available
Text: SN74ALVC16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JANUARY 1993 DGG OR DL PACKAGE TOP VIEW UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
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SN74ALVC16601
18-BIT
MIL-STD-883C,
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TC4042BP
Abstract: IS902
Text: TC4042BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042BP/TC4042BF QUAD CLOCKED "D" LATCH TC4042BP/BF contains four circuits of MD" type latches having common CLOCK input and POLARITY input. When POLARITY input is placed at "H" level, D input
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TC4042BP/BF
TC4042BP/TC4042BF
TC4042BP/BF
TC4042BP
IS902
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truth table inverter gate 74
Abstract: 74HC74
Text: 6. HOW TO R E A D MI L T Y PE LOGIC S Y M B O LS A ND TRUTH TA B L ES 6 -1 H o w to read M I L typo L o g ic S y m b o l* Tkble 6-1 shows the MIL type logic symbols used in high-speed CMOS IC This logical chart is based on M1L-STD-806B. Clocked inverters and transmission gates employ specific symbols.
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M1L-STD-806B.
HC-73
HC-74
truth table inverter gate 74
74HC74
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Untitled
Abstract: No abstract text available
Text: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A
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SN54ACT3641
SGBS309A
5962-9560801QYA
5962-9560801NXD
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Untitled
Abstract: No abstract text available
Text: f¡J PERICOM Product Features: Com mon Features: • PI74FCT16511 and PI74FCT162511 are high-speed, low power devices with high current drive. • Vcc = 5V +10% • Typical tsk o (Output Skew) < 250 ps, clocked mode
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PI74FCT16511
PI74FCT162511
56-pin
PI74FCT16511T
PI74FCT162511T
PS2080A
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Transmission gate IC
Abstract: MIL-STD-806B
Text: 6. HOW TO R E A D M I L T Y P E LOGIC S Y M B O L S A N D T R U T H T A B L E S 6-1 How to read M IL type Logic Sym bols Tkble 6-1 shows the MIL type logic symbols used in high-speed CMOS IC. This logic chart is based on MIL-STD-806B. Clocked inverters and transmission gate, employ specific symbols.
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MIL-STD-806B.
AC-30
Transmission gate IC
MIL-STD-806B
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Untitled
Abstract: No abstract text available
Text: Ordering number : EN8S6089A CMOS LSI No. 5K5089A SAXYO LC374100RP, RM-10/LC374100RP, RM-20LV 4 MEG 524288 words x 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC374100RP, RM-10 and LC374100RP, RM-20LV are 4 1 94304-bit M ask Program m able Read Only
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EN8S6089A
5K5089A
LC374100RP,
RM-10/LC374100RP,
RM-20LV
3192-DIP32
RM-10
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1 m preset
Abstract: No abstract text available
Text: SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F,W PIN CONFIGURATION 74 B 74LS B B,F,W PACKAGE INFUT » .E DESCRIPTION 3 v cc r^ D A T * a This monolithic circuit is a synchronous reversible up/down counter having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked
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1N3064
1 m preset
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CI 7473
Abstract: A10C SN74ABT7819
Text: SN74ABT7819 512 x 18 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS125B —JULY 1992 - REVISED AUGUST 1934 Microprocessor Interface Control Logic Programmable Almost-Full/Almost-Empty Flags Fast Access Times of 9 ns With a 50-pF Load and Simultaneous Switching Data
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SN74ABT7819
SCBS125B
50-pF
80-Pin
bl723
CI 7473
A10C
SN74ABT7819
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sf 127d
Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Text: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction
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SN74ABT3611
SCBS127D
120-Pin
132-Pin
Q103E1S
sf 127d
127D
IC51-1324-828
D103E
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MC889P
Abstract: MC723P MC700P mc723 pj 56 diode MC816P laputa MC816 uln series -driver
Text: as wfumops \' P L A S T IC M R T L MC700P/800P series M C723P • MC816P J-K flip-flop with a direct clear input in addition to the clocked inputs. CLOCKED INPUT ftPCJIATIM <1> U+KD t-D i l l 3 1 2 - S » 1 (5) 2 - * T [11 <3} 3 -a C Co ^
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MC700P/800P
MC723P
MC816P
MC889P
MC723P
MC700P
mc723
pj 56 diode
MC816P
laputa
MC816
uln series -driver
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SN74ACT7811
Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884
Text: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227A- FEBRUARY 1993 - REVISED JUNE 1994 Member of the Texas Instruments Wldebus Family * Input-Ready, Output-Ready, and Half-Full Flags Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be
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SN74ACT7881
SCAS227A-
SN74ACT7882,
SN74ACT7884,
SN74ACT7811
50-pF
68-Pin
80-Pin
D0-D17
SN74ACT7811
SN74ACT7881
SN74ACT7882
SN74ACT7884
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