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    CLOCK SYNCHRONIZATION Search Results

    CLOCK SYNCHRONIZATION Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation

    CLOCK SYNCHRONIZATION Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DIP28

    Abstract: PLCC28 TS68950 TS68951 TS68952 TS68952CFN TS68952CP programming controle system with c rc711
    Text: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS


    Original     		PDF TS68952 TS68952 TS68950 PLCC28 PMPLCC28 DIP28 TS68951 TS68952CFN TS68952CP programming controle system with c rc711

    TDC 8117

    Abstract: TS68952CP
    Text: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS


    Original     		PDF TS68952 TS68952 TS68950 TDC 8117 TS68952CP

    DS31400

    Abstract: APP4391 DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE phase failure protection IC
    Text: Maxim > App Notes > Communications circuits Keywords: stratum 3, stratum 3E, stratum 4E, G.813, G.812, clock, clock sync, clock synchronization, timing card, timing IC, DPLL, master- Apr 03, 2009 slave, redundancy, telecom, SONET, SDH, clock sync, sonet, sdh, equipment protection, synchronous ethernet


    Original     		PDF DS3105 DS3106 DS31400 14-Output, com/an4391 AN4391, APP4391, Appnote4391, APP4391 DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE phase failure protection IC

    APP4391

    Abstract: DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE
    Text: Maxim > App Notes > Communications Circuits T/E Carrier and Packetized Keywords: stratum 3, stratum 3E, stratum 4E, G.813, G.812, clock, clock sync, clock synchronization, timing card, timing IC, DPLL, master-slave, redundancy, telecom, SONET, SDH, clock sync, sonet, sdh, equipment


    Original     		PDF DS3104: DS3105: DS3106: com/an4391 AN4391, APP4391, Appnote4391, APP4391 DS3100 DS3101 DS3102 DS3104 DS3105 GR-1244-CORE

    ac phase ac 400 v detector

    Abstract: CY2210 CY2211
    Text: PRELIMINARY CY2211 Direct Rambus Clock Generator Features Benefits • High Speed Clock Support Provides 400-MHz differential clock source for Direct Rambus memory systems for an 800-MHz data transfer rate. • Synchronization Flexibility The CY2211 includes signals to synchronize the clock domains of the


    Original     		PDF CY2211 400-MHz 800-MHz CY2211 ac phase ac 400 v detector CY2210

    74AHCT193

    Abstract: SEL24 XRT8000 XRT8001 XRT8001ID XRT8001IP 128KHZT
    Text: XRT8001 WAN Clock for T1 and E1 Systems March 2001-1 • Generates Output Clock Frequencies Ranging GENERAL DESCRIPTION The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in


    Original     		PDF XRT8001 XRT8001 56kHz, 64kHz 54MHz 048MHz 64kHz 74AHCT193 SEL24 XRT8000 XRT8001ID XRT8001IP 128KHZT

    Untitled

    Abstract: No abstract text available
    Text: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in


    Original     		PDF XRT8001 XRT8001 56kHz, 64kHz 54MHz 048MHz

    SEL24

    Abstract: XRT8000 XRT8001 XRT8001ID XRT8001IP
    Text: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in


    Original     		PDF XRT8001 XRT8001 56kHz, 64kHz 54MHz 048MHz 64kHz SEL24 XRT8000 XRT8001ID XRT8001IP

    AT43USB320A

    Abstract: AT43USB325 AT43USB326 AT43USB351M AT43USB353M AT43USB355
    Text: Errata All Date Codes : Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated through the same crystal, the two clock sources are not going through the same


    Original     		PDF

    semi catalog

    Abstract: j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952
    Text: Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide 1 Clock Generator Data Sheets 2 QUICCClock Generator Data Sheets 3 Failover or Redundant Clock Data Sheets 4 Clock Synthesizer Data Sheets


    Original     		PDF DL207 xx/2004 semi catalog j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952

    transistor x1

    Abstract: IDT49FCT805 49FCT805A 49FCT806 AN-82 IDT49FCT805A IDT49FCT806 IDT74FCT244A
    Text: CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS  Integrated Device Technology, Inc. APPLICATION NOTE-82 CLOCK DISTRIBUTION SIMPLIFIED WITH IDT GUARANTEED SKEW CLOCK DRIVERS APPLICATION NOTE AN-82 By Michel Conrad INTRODUCTION WHAT IS CLOCK SKEW ?


    Original     		PDF NOTE-82 AN-82 50Mhz, AN-49" transistor x1 IDT49FCT805 49FCT805A 49FCT806 AN-82 IDT49FCT805A IDT49FCT806 IDT74FCT244A

    Untitled

    Abstract: No abstract text available
    Text: DATA SHEET ICS661 ICS661 Precision Audio Clock Source Precision Audio Clock Source Description Features The ICS661 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source


    Original     		PDF ICS661 ICS661 16-pin 199707558G

    ZL30155

    Abstract: KEY 10g zl3015 10GBASE-R simple block diagram for digital clock
    Text: DUAL CHANNEL UNIVERSAL CLOCK TRANSLATOR ZL30155 PRODUCT PREVIEW The ZL30155 Dual Channel Universal Clock Translator, part of Zarlink’s ClockCenter platform of Synchronous Clock devices, delivers industry-leading synchronization performance for high-speed complex applications. The highly integrated


    Original     		PDF ZL30155 ZL30155 OC-192/ STM-64/ 10GBase-W 10ZS054v6 KEY 10g zl3015 10GBASE-R simple block diagram for digital clock

    ZL30155

    Abstract: No abstract text available
    Text: DUAL CHANNEL UNIVERSAL CLOCK TRANSLATOR ZL30155 PRODUCT PREVIEW The ZL30155 Dual Channel Universal Clock Translator, part of Zarlink’s ClockCenter platform of Synchronous Clock devices, delivers industry-leading synchronization performance for high-speed complex applications. The highly integrated


    Original     		PDF ZL30155 ZL30155 OC-192/ STM-64/ 10GBase-W 10ZS197

    TDM 5510

    Abstract: 5501 7 segment
    Text: Application Note MSAN-171 TDM Clock Recovery from CBR-OverATM Links Using the MT90500 ISSUE 1 Contents 1. 2. 3. 4. 5. 6. 7. Introduction Plesiochronous Clock Applications Generalized Clock Recovery Synchronous Method Physical Layer Clock Adaptive Clock Recovery Method


    Original     		PDF MSAN-171 MT90500 TDM 5510 5501 7 segment

    DS21610

    Abstract: DS21610QN DS21610SN LXP610 TR62411 direct replacement
    Text: DS21610 Clock Rate Adapter www.maxim-ic.com FEATURES Direct replacement for LXP610SE Converts E-carrier clock rates to T-carrier clock rates Converts T-carrier clock rates to E-carrier clock rates Low jitter output Multiple output clocks synchronized to input


    Original     		PDF DS21610 LXP610SE 16-pin 28-pin DS21610SN DS21610QN DS21610 DS21610QN DS21610SN LXP610 TR62411 direct replacement

    M88TS

    Abstract: TS68952CFN TS68950-51-52 rca 210 BAT43 TS68950 TS68951 TS68952 rc711 ARC-3
    Text: S G S -T H O M S O N TS68952 !L [E O T riE @ [M D D Ì MODEM TRANSMIT/RECEIVE CLOCK GENERATOR • INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS ■ TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK


    OCR Scan     		PDF TS68952 TS68952 TS680/51/52 50-pins TS68930 M88TS TS68952CFN TS68950-51-52 rca 210 BAT43 TS68950 TS68951 rc711 ARC-3

    CH9073

    Abstract: No abstract text available
    Text: 101 CH9073 CHRONTEL Preliminary Video Genlock Pixel Clock Generator Features Description • On-chip PLL for clock synchronization CH 9073 is a PLL clock generator designed to provide the necessary implementation o f a video genlock pixel clock generator. It consists o f a phase detector, a charge


    OCR Scan     		PDF CH9073 CH9073 GG4133 CH9073A CH9073A-N CH9073A-S T0D4133 0DD01S2

    V20 70108

    Abstract: No abstract text available
    Text: UMC UM82C94 ^ S S S S S E CMOS Clock Generator Driver £ E Features • Generates the system clock for V-20 Microprocessor ■ Capable of clock synchronization with other clock ■ Up to 20 MHz operation generators ■ Uses a parallel mode crystal circuit or external frequency


    OCR Scan     		PDF UM82C94 UM82C94 100pF V20 70108

    Untitled

    Abstract: No abstract text available
    Text: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _SCAS379B - FEBRUARY 1993 - REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock


    OCR Scan     		PDF CDC2582 SCAS379B SCAS379B-FEBRUARY 6S5303»

    Untitled

    Abstract: No abstract text available
    Text: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994- REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vqc Distributes Differential LVPECL Clock


    OCR Scan     		PDF SCAS446B CDC582 52-Pin

    Untitled

    Abstract: No abstract text available
    Text: CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _ SCAS446B - JULY 1994 - REVISED FEBRUARY 1996 Low Output Skew for Clock-Dlstrlbutton and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock


    OCR Scan     		PDF CDC582 SCAS446B SS5303 7S266

    Untitled

    Abstract: No abstract text available
    Text: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS _SCAS379B- FEBRUARY 1993 - REVISED FEBRUARY 1996 • • Low Output Skew or Clock-Distrlbutlon and Clock-Generatlon Applications Operates at 3.3-V Vcc Distributes Differential LVPECL Clock


    OCR Scan     		PDF SCAS379B- CDC2582 52-Pin

    Untitled

    Abstract: No abstract text available
    Text: CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379 - FEBRUARY 1993 - REVISED MARCH 1994 Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V V cc Distributes Differential LVPECL Clock


    OCR Scan     		PDF CDC2582 SCAS379 PLH22 PLH23 PLH24