Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
20-Ppplication
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
20-Ppplication
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
20-Ppplication
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
20-Pd
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
20-Pstruments
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PDF
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CDC5806
Abstract: MTSS001C
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
CDC5806
MTSS001C
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PDF
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CDC5806
Abstract: CDC5806PW CDC5806PWR CDC5806PWRG4 MTSS001C
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
CDC5806
CDC5806PW
CDC5806PWR
CDC5806PWRG4
MTSS001C
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PDF
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CDC5806
Abstract: CDC5806PW CDC5806PWG4 CDC5806PWR CDC5806PWRG4 MTSS001C
Text: CDC5806 www.ti.com SCAS760A – MARCH 2004 – REVISED JULY 2004 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS FEATURES • • • • • • • • • • • High Performance Clock Generator Clock Input Compatible With LVCMOS/LVTTL Requires a 54-MHz Input Clock to Generate
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Original
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CDC5806
SCAS760A
54-MHz
Hz/54
Hz/12
Hz/19
CDC5806
CDC5806PW
CDC5806PWG4
CDC5806PWR
CDC5806PWRG4
MTSS001C
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PDF
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Untitled
Abstract: No abstract text available
Text: CDC5806 THREE PLLs BASED CLOCK GENERATOR FOR DIGITAL TV APPLICATIONS SCAS760A − MARCH 2004 − REVISED MAY 2004 features D High Performance Clock Generator D Clock Input Compatible With D D Max D PLLs are Powered Down, if No Valid D D D REF_IN Clock < 5 MHz) is Detected or the
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CDC5806
SCAS760A
54-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCD5704 www.ti.com SCAS823A – DECEMBER 2006 – REVISED JANUARY 2008 Rambus XDR™ CLOCK GENERATOR FEATURES 1 • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface • Quad Open-Drain Differential Output Drivers
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CDCD5704
SCAS823A
300-MHz
667-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCD5704 www.ti.com SCAS823A – DECEMBER 2006 – REVISED JANUARY 2008 Rambus XDR™ CLOCK GENERATOR FEATURES 1 • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface • Quad Open-Drain Differential Output Drivers
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CDCD5704
SCAS823A
300-MHz
667-MHz
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCE949-Q1 www.ti.com SCAS891 – FEBRUARY 2010 PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS Check for Samples: CDCE949-Q1 FEATURES 1 • • • • Qualified for Automotive Applications Member of Programmable Clock Generator
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CDCE949-Q1
SCAS891
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949:
IEEE139p
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PDF
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SSC31
Abstract: fs37 SSC3020 CDCE949 CDCE949QPWRQ1 ssc-32 SSC16 ssc24 SSC3120
Text: CDCE949-Q1 www.ti.com SCAS891 – FEBRUARY 2010 PROGRAMMABLE 4-PLL VCXO CLOCK SYNTHESIZER WITH 1.8-V, 2.5-,V and 3.3-V LVCMOS OUTPUTS Check for Samples: CDCE949-Q1 FEATURES 1 • • • • Qualified for Automotive Applications Member of Programmable Clock Generator
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CDCE949-Q1
SCAS891
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949:
SSC31
fs37
SSC3020
CDCE949
CDCE949QPWRQ1
ssc-32
SSC16
ssc24
SSC3120
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCE949 CDCEL949 www.ti.com SCAS844D – AUGUST 2007 – REVISED MARCH 2010 Programmable 4-PLL VCXO Clock Synthesizer with 1.8V, 2.5V and 3.3V LVCMOS Outputs Check for Samples: CDCE949, CDCEL949 FEATURES • 1 • Member of Programmable Clock Generator Family
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CDCE949
CDCEL949
SCAS844D
CDCE949,
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949/CDCEL949:
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PDF
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CDCE913
Abstract: CDCEL913
Text: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator
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CDCEL913-Q1
SCAS888
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949/CDCEL949:
CDCE913
CDCEL913
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator
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Original
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CDCEL913-Q1
SCAS888
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949/CDCEL949:
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs Check for Samples: CDCEL913-Q1 FEATURES 1 • • • • • • • Qualified for Automotive Applications Member of Programmable Clock Generator
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CDCEL913-Q1
SCAS888
CDCE913/CDCEL913:
CDCE925/CDCEL925:
CDCE937/CDCEL937:
CDCE949/CDCEL949:
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PDF
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B0137
Abstract: No abstract text available
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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CDCD5704
SCAS823
300-MHz
667-MHz
B0137
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PDF
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B0137
Abstract: No abstract text available
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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Original
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CDCD5704
SCAS823
300-MHz
667-MHz
B0137
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PDF
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Untitled
Abstract: No abstract text available
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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CDCD5704
SCAS823
300-MHz
667-MHz
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PDF
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Rambus XDR
Abstract: CDCD5704 TSSOP-28 t0132
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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CDCD5704
SCAS823
300-MHz
667-MHz
Rambus XDR
CDCD5704
TSSOP-28
t0132
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PDF
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XDR Rambus
Abstract: CDCD5704 TSSOP-28 B0137
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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Original
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CDCD5704
SCAS823
300-MHz
667-MHz
XDR Rambus
CDCD5704
TSSOP-28
B0137
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PDF
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CDCD5704
Abstract: TSSOP-28 t0132 B0137
Text: CDCD5704 www.ti.com SCAS823 – DECEMBER 2006 Rambus XDR™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • High-Speed Clock Support: 300-MHz–667-MHz Clock Source for XDR Memory Subsystems and Redwood Logic Interface Quad Open-Drain Differential Output Drivers
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Original
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CDCD5704
SCAS823
300-MHz
667-MHz
CDCD5704
TSSOP-28
t0132
B0137
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PDF
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