files
Abstract: Users
Text: CyClocks support software for Programmable Clock Generators clksetup.exe clk34200.exe readme This is a self-extracting zipped file containing all of the installation files for CyClocks ver3.42. This has only the executable and help files zipped in. Users who have CyClocks ver2 or higher on
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clk34200
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Untitled
Abstract: No abstract text available
Text: M63160J STEPPING MOTOR DRIVER REJ03F0038-0110Z Rev.1.1 May.21.2004 Description This semiconductor integrated circuit includes for H bridge circuit for stepper Motor drive.Output transistor is DMOS. Motor power supply;is possible to drive until 52V maximum.
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M63160J
REJ03F0038-0110Z
20MHz
CLK12
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Untitled
Abstract: No abstract text available
Text: MSP-EXP430G2 LaunchPad Evaluation Kit User's Guide Literature Number: SLAU318E July 2010 – Revised March 2014 Contents . 4 . 4
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MSP-EXP430G2
SLAU318E
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SL127L6TH
Abstract: CAT24FC32UI "mini usb connector" MSP-EXP430G2 thermistor ntc 100r FR57XX MSP430F2274 EXP-MSP430F5438 low power tilt sensor using msp430 FR57XX-RHA40RHAPACKAGE
Text: MSP-EXP430FR5739 FRAM Experimenter Board User's Guide Literature Number: SLAU343B May 2011 – Revised February 2012 2 SLAU343B – May 2011 – Revised February 2012 Submit Documentation Feedback Copyright 2011–2012, Texas Instruments Incorporated Contents
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MSP-EXP430FR5739
SLAU343B
SLAU343B
SL127L6TH
CAT24FC32UI
"mini usb connector"
MSP-EXP430G2
thermistor ntc 100r
FR57XX
MSP430F2274
EXP-MSP430F5438
low power tilt sensor using msp430
FR57XX-RHA40RHAPACKAGE
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Untitled
Abstract: No abstract text available
Text: AMD Geode CS5536 Companion Device Data Book May 2007 Publication ID: 33238G AMD Geode™ CS5536 Companion Device Data Book 2007 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro
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CS5536
33238G
CS5536
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Untitled
Abstract: No abstract text available
Text: Ordering number : ENN7944 Bi-CMOS IC Seven-Channel Motor Driver IC for Digital Cameras LV8041FN Overview The LV8041FN is a digital camera motor driver IC that integrates seven driver channels on a single chip. Features • Two PWM current control microstepping drive stepping motor driver channels
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ENN7944
LV8041FN
LV8041FN
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Untitled
Abstract: No abstract text available
Text: ASAHI KASEI EMD CORPORATION Low Power Multiclock Generator with VCXO AK8131C Features Description 27MHz Crystal Input Clock out Frequencies: REFOUT: 27.000MHz CLK1: 33.000MHz CLK2: 33.000MHz CLK3: 27.000MHz CLK4: 27.000MHz The AK8131C is a member of AKEMD’s low power
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AK8131C
27MHz
000MHz
100ppm
16-pin
AK8131C
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SSSU
Abstract: S12CPU15UG HCS12 M68HC11 object counter IH145 1488 standard F80F 3BF3 TP328
Text: DOCUMENT NUMBER S12CPU15UG/D HCS12 V1.5 Core User Guide Version 1.2 Original Release Date: 12 May 2000 Revised: 17 August 2000 Motorola, Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
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S12CPU15UG/D
HCS12
S12CPU15UG
SSSU
M68HC11
object counter
IH145
1488 standard
F80F
3BF3
TP328
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Untitled
Abstract: No abstract text available
Text: CMOSリニアイメージセンサ S12443 画素サイズ: 7 x 125 m2496画素、小型パッケージ S12443は、小型でありながら2496画素で長尺の受光面 有効受光面長 17.472 mm をもったCMOSリニアイメージセンサ です。画素サイズは 7 × 125 μmです。
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S12443
S12443ã
KMPD1137J05
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OQ8866
Abstract: lo9585 53CF94 53c90 A1266 BPA 12 V radial Ras 1210 80C32 SAA7385 SAA7385GP
Text: INTEGRATED CIRCUITS DATA SHEET SAA7385 Error correction and host interface IC for CD-ROM SEQUOIA Preliminary specification File under Integrated Circuits, IC01 1996 Jun 19 Philips Semiconductors Preliminary specification Error correction and host interface IC
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SAA7385
53CF94
SCA49
517021/50/01/pp64
OQ8866
lo9585
53c90
A1266
BPA 12 V radial
Ras 1210
80C32
SAA7385
SAA7385GP
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CLK12
Abstract: LV8042LG LV-S61 stepping motor 35 st-25
Text: Ordering number : ENA0004A LV8042LG Bi-CMOS IC For Digital Still Cameras 7-Channel Single-Chip Motor Driver ICs Overview The LV8042LG is Motor driver 7ch single-chip for DSC. Features • Micro-step driven stepping motor driverx2 • PWM driven forward/reverse motor driver
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ENA0004A
LV8042LG
LV8042LG
A0004-29/29
CLK12
LV-S61
stepping motor 35 st-25
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SASI
Abstract: cmps a13 grd 07 z32106 Z32100 IRR28 we32100
Text: Zilog P roduct S pecification January 1987 / O D ^ O ^ Z32106 M A U M A T H A C C E L E R A T IO N U N IT DESCRIPTION T he Z32106 M ath A cceleration U nit M AU provides floating-point capability fo r the Z32100 M icroprocessor and is fully com patible with
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Z32106
Z32100
32bit)
64-bit)
80-bit)
32-bit
125-pin
SASI
cmps a13
grd 07
IRR28
we32100
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Z32100
Abstract: z32104
Text: Zilog P r o du c t S p e c i f i c a t i o n J a n u a ry 1987 /oc€>o4 Z32104 D M A C O N TR O LL ER D ESCRIPTIO N T h e Z32104 D M A C o n tro lle r D M A C is a m em ory-m apped p e rip h e ra l device th a t p erfo rm s m em ory-to-m em ory, m em ory-to-peripheral, and
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Z32104
Z32100
32-bit
133-pin
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a00u
Abstract: Z32100 STK 411 230 WE32100 ALI m7 101b BUX 707 z32101 Z32103 BUDA lo4p
Text: Y " P ro d u ct S pecification January 1987 Z32103 D R A M C O N TR O LLER DESCRIPTION T he Z32103 D R A M Controller provides address multiplexing, access and cycle time management, and refresh control for dynam ic random access m emory DRAM . It provides, in a single chip,
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Z32103
32-bit
a00u
Z32100
STK 411 230
WE32100
ALI m7 101b
BUX 707
z32101
BUDA
lo4p
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WE32101
Abstract: we32100 tC23E oxbe
Text: WE 32100 Microprocessor Description The WE 32100 Microprocessor CPU is a highperformance, single-chip, 32-bit central processing unit designed for efficient operation in a high-level language environment. It performs all the system address generation, control, memory access, and
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32-bit
32-bit)
16-bit)
225pF)
WE32101
we32100
tC23E
oxbe
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WE32104
Abstract: we32100 DMAC
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a memory-mapped peripheral device that performs memory-to-memory, memory fill, memory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32104
we32100
DMAC
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we32100
Abstract: No abstract text available
Text: WE 32106 Math Acceleration Unit Description The WE 32106 Math Acceleration Unit MAU provides floating-point capability for the WE 32100 Microprocessor and is fully compatible with the IEEE Standard for Binary FloatingPoint Arithmetic (ANSI/IEEE Std. 754-1985). It
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32-bit)
64-bit)
80-bit)
32-bit
18-MHz
we32100
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z32100
Abstract: LK23
Text: Zilog P ro du ct Specification January 1987 /£ > 3 0 3 3 Z32101 MEMORY MANAGEMENT UNIT DESCRIPTION T he Z32101 M emory M anagem ent U nit MMU is a 32-bit bus-structured device that provides logicalto-physical address translation, memory organization, control, and access protection for
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Z32101
32-bit
Z32100
LK23
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TAC01
Abstract: No abstract text available
Text: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD F eatures F unctional D escription • 64 MAX macrocells in 4 LABs The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible
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CY7C343
44-pin
64-Macrocell
CY7C343
CY7C343--
30HC/HI
CY7C343-30JC/JI
TAC01
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IC ATA 2388
Abstract: ATA 2388 we32100 YXXXX
Text: WE 32106 M ath A cceleratio n Unit Description The W E 32 10 6 M a th A c c e le ra tio n U n it MAU pro vid e s flo a tin g -p o in t c a p a b ility fo r th e WE 32100 M ic ro p ro c e s s o r a n d is fu lly co m p a tib le w ith th e IEEE S ta n d a rd fo r B in ary F lo a tin g
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WE32101
Abstract: XORB eisc oxc7 0B11-R TC292
Text: W E 32100 M icrop ro c es s o r Description The W E 32100 M ic ro p ro c e s s o r CPU is a h ig h p e rfo rm a n ce , s in g le -c h ip , 3 2 -b it cen tra l pro cessing u n it de sig ned fo r e ffic ie n t o p e ra tio n in a high -leve l la n g u a g e en viro n m e n t. It pe rfo rm s all the system
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32-bit
32-bit)
16-bit)
225pF)
WE32101
XORB
eisc
oxc7
0B11-R
TC292
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DRAM Controller
Abstract: 112-12a 100C we32100 8 bit dRAM Controller we32103
Text: WE 32103 DRAM Controller Description The WE 32103 DRAM C ontroller provides address m ultiplexing, access and cycle time management, and refresh control fo r dynamic random access memory DRAM . In a single chip, it provides the interface between high
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32-bit
18-MHz
125-pin
DRAM Controller
112-12a
100C
we32100
8 bit dRAM Controller
we32103
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Untitled
Abstract: No abstract text available
Text: fax id: 6102 CY7C343 CY7C343B 64-Macrocell MAX EPLD Functional Description Featu res • 64 MAX macrocells in 4 LABs • 8 dedicated inputs, 24 bidirectional I/O pins • Programmable interconnect array The CY7C343/CY7C343B is a high-performance, high-density erasable programmable logic device, available in 44-pin
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CY7C343
CY7C343B
64-Macrocell
CY7C343)
65-micron
CY7C343B)
44-pin
CY7C343/CY7C343B
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BY90
Abstract: z32100 z32102
Text: Zilog P ro d u c t S p ecificatio n January 1987 / o o 2 &3 Z32102 CLOCK DESCRIPTION T he Z32102 Clock supplies the two-phase, CMOSlevel frequency source required by the Z32100 Microsystem. T he Z32102 Clock generates three outputs from a crystal controlled encoder. Two of
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Z32102
Z32100
BY90
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