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    7213-37

    Abstract: No abstract text available
    Text: S G S-THOHSON Q7E DB .6 7C 1 6 Z 6 6 ? ‘Ì E CI537 DQlblB? 4 • AC WAVEFORMS continued Fig. 4 Set-Up Tim e (ts) and Hold (t^,) for Parallel Data Inputs Fig. 3 Clock to Terminal Delays \ J uv J WO ) h-'HX f/ 7 ,/////// / Fig. 5 Set-Up tim e (ts) and hold tim e th) for


    OCR Scan     		PDF T54LS170 T74LS170 7213-37

    MC34060

    Abstract: MC 34060 P 34060
    Text: S-THOMSON 7 AC D I ? T 2 ci537 000ti3ñ7 78C 06387 ^ Ç • T ~ f Z '/ t - 3 l “ MC34060 PULSE WIDTH MODULATION CONTROL CIRCUIT PULSE W IDTH MODULATION CONTROL CIRCUIT The MC34060 DP Is a low cost fixed frequency, pulse width modulation con­ trol circuit designed primarily for single ended SW ITCH M O DE power supply


    OCR Scan     		PDF 000ti3 MC34060 MC34060 MC 34060 P 34060

    S67C

    Abstract: T54l
    Text: s G S-THOnsON D7E » ? T 2 ci537 GOlSiôt, 0 LOW POWER SGHÔTTKY 67C 16111 INTEGRATED CIRCUITS D T -4 ù>-ô 7~£>7 PRELIMINARY DATA DUAL JK FLIP-FLOP WITH SET AND CLEAR D ESC RIPTIO N The T54LS/T74LS76A dual flip-flops feature sepa­ rate J, K, Clock Pulse, Direct Set and Direct Clear


    OCR Scan     		PDF T54LS/T74LS76A T74LS76A T54LS76A S67C T54l

    Untitled

    Abstract: No abstract text available
    Text: n $ î. SGS-THOMSON IMDIêœiLIKêraRilDIgi L6260 2.7 - 5.5V DISK DRIVER SPINDLE & VCM, POWER & CONTROL COMBO’S PRODUCT PREVIEW GENERAL • 5V AND 3V OPERATION. ‘ REGISTER BASED ARCHITECTURE . MINIMUM EXTERNAL COMPONENTS ■ SLEEP AND IDLE MODES FOR LOW


    OCR Scan     		PDF L6260 300mA TQFP64

    GI 9340

    Abstract: f9341 modulo 10 counter F9340 TTL latch ic
    Text: S G S- THOnSON 7ÖC D I □ □ Û7 □ 5 4 T EF9340 EF9341 AD VANCE INFORMATION MOS N -C H A N N E L ,S IL IC O N G ATE f S EM I-G R A P H IC C R T D IS P L A Y PROCESSOR Tw o 40 pin circuits EF9340 (VIN ) and EF9341 (GEN) and 16 K bits o f standard static RAM are enough to build a complete semi-graphic


    OCR Scan     		PDF EF9340 EF9341 EF9340 F9340 00070fll T-52-33-09 CB-182 GI 9340 f9341 modulo 10 counter F9340 TTL latch ic

    ALTERA EP

    Abstract: I7232 MIL-STD-883-compliant
    Text: EP1810 EPLD Features • High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD as low as 20 ns Counter frequencies of up to 50 MHz Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs The following devices are pin-, function-, and programming filecompatible: EP1810, EP1810T, and EP1810 MIL-STD-883-compliant


    OCR Scan     		PDF EP1810 48-macrocell EP1810, EP1810T, MIL-STD-883-compliant 68-pin ALTERA EP I7232

    9829B

    Abstract: EPM7096 EPM7096-10 EPM7096-12 EPM7096-7 d4454 EPM7096 QFP DATA
    Text: ALTERA CORP bflE ]> • 05^5372 0003E3b T34 « A L T EPM 7096 EPLD Features □ P re lim in a ry □ □ □ I n f o r m a t io n □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 1,800 usable gates Combinatorial speeds with tPD = 7.5 ns


    OCR Scan     		PDF 0003E3b EPM7096 84-pin 100-pin qua24 0QQ3243 68-Pin 9829B EPM7096-10 EPM7096-12 EPM7096-7 d4454 EPM7096 QFP DATA

    marking g1

    Abstract: marking HA 7 sot23 transistor bfs20 BFS20
    Text: rZ 7 SGS-THOMSON WiCTOOieS BFS20 SMALL SIGNAL NPN TRANSISTOR Type Marking BFS20 G1 . SILICON EPITAXIAL PLANAR NPN TRANSISTORS . MINIATURE PLASTIC PACKAGE FOR APPLICATION IN SURFACE MOUNTING CIRCUITS . COMMON EMITTER IF AMPLIFIER SOT-23 ABSOLUTE MAXIMUM RATINGS


    OCR Scan     		PDF BFS20 OT-23 OT-23 marking g1 marking HA 7 sot23 transistor bfs20 BFS20

    ns4248

    Abstract: ST6210B6 7TET53 marking s17 SON st1548 ST6215B1
    Text: r z ^ 7 S G S -T H O M S O N 7 # S T 6 2 1 0 -S T 6 2 1 5 S T 6 2 2 0 -S T 6 2 2 5 8-BIT HCMOS MCUs WITH A/D CONVERTER • 3.0 to 6.0V Supply Operating Range ■ 8 MHz Maximum Clock Frequency ■ -40 to +85‘C Operating Temperature Range ■ Run, Wait & Stop Modes


    OCR Scan     		PDF ST6210 ST6220 PDIP20, PS020 PDIP28, PS028 ST6215 upT6225 ns4248 ST6210B6 7TET53 marking s17 SON st1548 ST6215B1

    Untitled

    Abstract: No abstract text available
    Text: S G S -T H O M S O N ST95081 H 0 g lM S iH i ! i3 © f f l( g § _ SERIAL ACCESS SPI BUS 8K (1024 x 8 EEPROM PRELIMINARY DATA • 100,000 ERASE/WRITE CYCLES ■ 10 YEARS DATA RETENTION ■ SINGLE 4.5V to 5.5V SUPPLY VOLTAGE ■ SPI BUS COMPATIBLE SERIAL INTERFACE


    OCR Scan     		PDF ST95081 ST95081 7TETE37 QD72231 7T2T237

    Untitled

    Abstract: No abstract text available
    Text: S G S-THOHSON 07C D | 7TSTE3? 0014MS3 43C 11 F I F O In p u t/ O u tp u l In t e r f a c e u n it Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or C PU /peripheral interface, expandable to any width in byte increm ents by use of m ultiple Z8060 FIO 's


    OCR Scan     		PDF 0014MS3 128-byte Z8060 Z8538 Z8538 -i-70oC -40/-i-85oC Z8538Ã