AHC1G04
Abstract: SN74AHC1G04H
Text: SN74AHC1G04 SINGLE INVERTER GATE SCLS318Q − MARCH 1996 − REVISED JUNE 2005 D D D D D Schmitt Trigger Action at All Inputs Makes Operating Range of 2 V to 5.5 V Max tpd of 6.5 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V D
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SN74AHC1G04
SCLS318Q
sgyc003d
scyb017a
scla013d
sgyn133
sgyv014c
AHC1G04
SN74AHC1G04H
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military radar 20 pages documentation
Abstract: SN74LVTH373-EP
Text: SN74LVTH373ĆEP 3.3ĆV ABT OCTAL TRANSPARENT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCBS770 − NOVEMBER 2003 D Controlled Baseline D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing
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SN74LVTH373EP
SCBS770
000-V
military radar 20 pages documentation
SN74LVTH373-EP
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CI 4835 b
Abstract: No abstract text available
Text: SN74AC32ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCAS720 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of
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SN74AC32EP
SCAS720
CI 4835 b
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cmos testing abstract
Abstract: No abstract text available
Text: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot
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SN74ACT1071
10-BIT
SCAS192
D3994,
MIL-STD-883C,
scyd013
sdyu001x
sgyc003d
scyb017a
cmos testing abstract
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Untitled
Abstract: No abstract text available
Text: SN74BCT757 OCTAL BUFFER/DRIVER WITH OPEN-COLLECTOR OUTPUTS SCBS041D – NOVEMBER 1989 – REVISED NOVEMBER 1993 • • • • DW OR N PACKAGE TOP VIEW BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds
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SN74BCT757
SCBS041D
MIL-STD-883C,
300-mil
sdyu001x
sgyc003d
scyb017a
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Untitled
Abstract: No abstract text available
Text: SN74AC04ĆEP HEX INVERTER SCAS717 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources DMS Support Enhanced Product-Change Notification
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SN74AC04EP
SCAS717
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Untitled
Abstract: No abstract text available
Text: SN74AC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATE SCAS718 − OCTOBER 2003 D Controlled Baseline D D D D D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of
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SN74AC08EP
SCAS718
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newark
Abstract: AHC1G08 TAS5066-5121K6EVM
Text: SN74AHC1G08 SINGLE 2ĆINPUT POSITIVEĆAND GATE SCLS314M − MARCH 1996 − REVISED JUNE 2005 D D D D D D Latch-Up Performance Exceeds 250 mA Per Operating Range of 2 V to 5.5 V Max tpd of 7 ns at 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 5 V
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SN74AHC1G08
SCLS314M
000-V
A114-A)
A115-A)
scla013d
sgyn133
sgyv014c
TAS5066-5121K6
newark
AHC1G08
TAS5066-5121K6EVM
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Untitled
Abstract: No abstract text available
Text: [ /Title CD54H C08, CD54H CT08, CD74H C08, CD74H CT08 /Subject (High CD54HC08, CD74HC08, CD54HCT08, CD74HCT08 Data sheet acquired from Harris Semiconductor SCHS118C High-Speed CMOS Logic Quad 2-Input AND Gate August 1997 - Revised July 2004 Features Description
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CD54HC08,
CD74HC08,
CD54HCT08,
CD74HCT08
SCHS118C
CD74HCT08
74HCT
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74hc30
Abstract: No abstract text available
Text: [ /Title CD54H C30, CD74H C30, CD74H CT30 /Subject (High Speed CMOS Logic 8- CD54/74HC30, CD54/74HCT30 Data sheet acquired from Harris Semiconductor SCHS121D High Speed CMOS Logic 8-Input NAND Gate August 1997 - Revised September 2003 Features Description
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CD54/74HC30,
CD54/74HCT30
SCHS121D
HCT30
CD54H
CD74H
74hc30
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Untitled
Abstract: No abstract text available
Text: SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series
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SN74HSTL162822
14-BIT
28-BIT
SCES091A
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Untitled
Abstract: No abstract text available
Text: SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications
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SN74HSTL16918
18-BIT
SCES096C
MIL-STD-883,
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nom 8370 b
Abstract: No abstract text available
Text: 74AC11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATE www.ti.com SCLS054B – APRIL 1987 – REVISED JUNE 2005 FEATURES • • • • D OR N PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
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74AC11000
SCLS054B
500-mA
300-mil
scyd013
sdyu001x
sgyc003d
scyb017a
nom 8370 b
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Untitled
Abstract: No abstract text available
Text: 74AC11004 HEX INVERTER SCAS033B – JANUARY 1988 – REVISED APRIL 1996 D D D D D DB, DW, OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted
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74AC11004
SCAS033B
500-mA
300-mil
scyd013
sdyu001x
sgyc003d
scyb017a
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Untitled
Abstract: No abstract text available
Text: SN74HSTL16919 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS SCES348 – MARCH 2001 D D D D D DGG PACKAGE TOP VIEW Member of Texas Instruments’ Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6, and Outputs Meet Level III Specifications
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SN74HSTL16919
18-BIT
SCES348
000-V
A114-A)
A115-A)
sced006b
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Untitled
Abstract: No abstract text available
Text: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for
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SN74S1051
12-BIT
SDLS018B
scyd013
sdyu001x
sgyc003d
scyb017a
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Untitled
Abstract: No abstract text available
Text: SN74AHCT1G32ĆQ1 SINGLE 2ĆINPUT POSITIVEĆOR GATE SCLS606A − MARCH 2005 − MARCH 2005 D Qualification in Accordance With DBV OR DCK PACKAGE TOP VIEW AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D
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SN74AHCT1G32Q1
SCLS606A
AEC-Q100
AEC-Q100
000-V
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Untitled
Abstract: No abstract text available
Text: [ /Title CD74 HC86, CD74 HCT86 /Subject (High Speed CMOS Logic Quad 2-Input EXCL USIVE OR CD54HC86, CD74HC86, CD54HCT86, CD74HCT86 Data sheet acquired from Harris Semiconductor SCHS137D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE-OR Gate August 1997 - Revised September 2003
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CD54HC86,
CD74HC86,
CD54HCT86,
CD74HCT86
SCHS137D
HCT86
HCT86
scdd003a
scyd013
sdyu001x
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Untitled
Abstract: No abstract text available
Text: SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE TOP VIEW Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for
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SN74S1051
12-BIT
SDLS018B
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Untitled
Abstract: No abstract text available
Text: SN64BCT125A QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCBS052B – JULY 1990 – REVISED MAY 1994 • • • • • D OR N PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ High-Impedance State During Power-Up and Power-Down
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SN64BCT125A
SCBS052B
MIL-STD-883C
300-mil
scyd013
sdyu001x
sgyc003d
scyb017a
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Untitled
Abstract: No abstract text available
Text: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A – MARCH 1992 – REVISED NOVEMBER 2002 D D D D D D D D D DW OR NS PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation
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SN74ACT1073
16-BIT
SCAS193A
000-V
A114-A)
A115-A)
scyd013
sdyu001x
sgyc003d
scyb017a
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Untitled
Abstract: No abstract text available
Text: SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D D D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB
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SN74SSTL16847
20-BIT
SCBS709A
MIL-STD-883,
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transistor data book free
Abstract: transistor data book free download CI 4835 b Cross ReferenceTransistor Book all transistor data sheet book download
Text: SN74TVC3306 DUAL VOLTAGE CLAMP www.ti.com SCDS112C – MARCH 2001 – REVISED MARCH 2005 FEATURES • DCT OR DCU PACKAGE TOP VIEW Designed to Be Used in Voltage-Limiting Applications 3.5-Ω On-State Connection Between Ports A and B Flow-Through Pinout for Ease of Printed
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SN74TVC3306
SCDS112C
000-V
A114-A)
A115-A)
scdm002a
sdyu001x
scyb017a
transistor data book free
transistor data book free download
CI 4835 b
Cross ReferenceTransistor Book
all transistor data sheet book download
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Ic 7442
Abstract: No abstract text available
Text: S C IE N TIF IC / M I N I - C I R C U IT S 4RE D • fiO b B B ll 000 13 4 7 f l S l H S C C plug-in, surface-m ount Frequency Mixers Models t-74-°9-01 I CV/CI -7 F-3 TUF-3SM L tV tL / + 7 dBm LO, up to +1 dBm RF computer-automated performance data typical production unit / for data of other models consult factory
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