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    CHAIN LINKAGE Search Results

    CHAIN LINKAGE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    L17D4K63037 Amphenol Communications Solutions Flat Male Dust Cover with Chain, C size for Standard 37 pin and High Density 62 pin, for Use for Female connector Visit Amphenol Communications Solutions
    L17D4K63026 Amphenol Communications Solutions Flat Male Dust Cover without Chain, B size for Standard 25 pin and High Density 44 pin, for Use for Female connector Visit Amphenol Communications Solutions
    L17D4K63015 Amphenol Communications Solutions Flat Male Dust Cover with Chain, A size for Standard 15 pin and High Density 26 pin, for Use for Female connector Visit Amphenol Communications Solutions
    L17D4K63125 Amphenol Communications Solutions Flat Female Dust Cover with Chain, B size for Standard 25 pin and High Density 44 pin, for Use for Male connector Visit Amphenol Communications Solutions
    L17D4K63050 Amphenol Communications Solutions Flat Male Dust Cover with Chain, D size for Standard 50 pin and High Density 78 pin, for Use for Female connector Visit Amphenol Communications Solutions

    CHAIN LINKAGE Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: APPLICATION NOTE H8S/2200 Series DTC Transfer Activation by 8-Bit Timer Channel 0A Interrupt, Examples of Using Chain Function Introduction Transfers data on an SRAM chip to other addresses on the chip with the DTC that is activated by the 8-bit timer channel 0A interrupt. It also transfers data continuously to other addresses on the SRAM chip with the DTC chain


    Original     		PDF H8S/2200 H8S/2215 REJ06B0349-0100Z/Rev

    CHN 623 Diodes

    Abstract: MACHpro vantis jtag schematic module bsm 25 gp 120 MACH445 MACH Programmer 7265 L1210 mach 1 family amd CHN 623 diode BSM 225
    Text: 11 CHAPTER 1 Chapter 1 Introduction What is In-System Programming ISP ? Before In-System Programming (ISP) was developed, programming complex programmable logic devices (CPLDs) was a tedious process. After creating the JEDEC fuse map files with design automation software, designers or manufacturing engineers have to insert the CPLDs into


    Original     		PDF

    7265-PC-0002

    Abstract: 21554 CHN 623 Diodes Vantis ISP cable 208pin PQFP L1210 eeprom programmer schematic 74ls244 MACH445 teradyne 93-009-6105-JT-01
    Text: 11 CHAPTER 1 Chapter 1 Introduction What is In-System Programming ISP ? Before In-System Programming (ISP) was developed, programming complex programmable logic devices (CPLDs) was a tedious process. After creating the JEDEC fuse map files with design automation software, designers or manufacturing engineers have to insert the CPLDs into


    Original     		PDF

    Xilinx jtag cable hardware user guide

    Abstract: ieee 1532 PAD123 BSDL P103 P104 P105 P112 P206 PQ208
    Text: Application Note: Spartan-3 FPGA Series R Using BSDL Files for Spartan-3 Generation FPGAs XAPP476 v1.1 June 19, 2005 Summary BSDL (Boundary Scan Description Language) files are provided for every part and package combination of IEEE 1149.1 (JTAG) compatible devices produced by Xilinx, including all the


    Original     		PDF XAPP476 Xilinx jtag cable hardware user guide ieee 1532 PAD123 BSDL P103 P104 P105 P112 P206 PQ208

    TSB11C01

    Abstract: TSB12LV21 pcilynx TSB11LV01 TSB12C01A TSB12LV21A TSB14C01 TSB21LV03 TSB21LV03A 0xA30
    Text: Initialization and Asynchronous Programming of the PCILynx TSB12LV21A 1394 Device APPLICATION REPORT: SLLA023 Danny Mitchell BuS Solutions Software Group Mixed Signal and Logic Products BuS Solutions Group 15 December 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any


    Original     		PDF TSB12LV21A SLLA023 TSB11C01 TSB12LV21 pcilynx TSB11LV01 TSB12C01A TSB14C01 TSB21LV03 TSB21LV03A 0xA30

    uPD72001 users manual

    Abstract: uPD72001 manual PD72001 d70116 d71059 uPD7210 uPD72103 S10766E d71082 PD72103
    Text: µPD72103A HDLC CONTROLLER µPD72103A 1997 Document No. S10766EJ9V0UM00 9th edition Date Published March 1997 N CP(N) Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and


    Original     		PDF PD72103A S10766EJ9V0UM00 uPD72001 users manual uPD72001 manual PD72001 d70116 d71059 uPD7210 uPD72103 S10766E d71082 PD72103

    intel 27884

    Abstract: intel 31154 bsdl
    Text: Intel BSDL Validation on a 31154 133MHz PCI Bridge Application Note October 2003 Order Number: 278843-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN


    Original     		PDF 133MHz intel 27884 intel 31154 bsdl

    TSB11C01

    Abstract: 0xA18 TMS320 TSB11LV01 TSB12C01A TSB12LV21 TSB12LV21A TSB14C01 TSB21LV03 TSB21LV03A
    Text: Initialization and Asynchronous Programming of the PCILynx TSB12LV21A 1394 Device APPLICATION REPORT: SLLA023 Danny Mitchell BuS Solutions Software Group Mixed Signal and Logic Products BuS Solutions Group 15 December 1997 IMPORTANT NOTICE Texas Instruments TI reserves the right to make changes to its products or to discontinue any


    Original     		PDF TSB12LV21A SLLA023 TSB11C01 0xA18 TMS320 TSB11LV01 TSB12C01A TSB12LV21 TSB14C01 TSB21LV03 TSB21LV03A

    simple LFSR in built in self test

    Abstract: SCANSTAEVK verilog code 8 bit LFSR vhdl code 16 bit LFSR SCANSTA101 SCANSTA111 SCANSTA112 SCANSTA476 jtag cable Schematic corelis PADS-POWERPCB-V2007
    Text: SCANSTA101 STA Master Design Guide 2010 Revision 1.0 Developing a System with Embedded IEEE 1149.1 Boundary-Scan Self-Test national.com/scan Table of Contents Acknowledgements. 4


    Original     		PDF SCANSTA101 simple LFSR in built in self test SCANSTAEVK verilog code 8 bit LFSR vhdl code 16 bit LFSR SCANSTA111 SCANSTA112 SCANSTA476 jtag cable Schematic corelis PADS-POWERPCB-V2007

    h8sx

    Abstract: No abstract text available
    Text: APPLICATION NOTE H8SX Family DTC Block Transfer Introduction This application note describes using the data transfer controller DTC function to transfer five blocks of data, each comprising two bytes, and outputting the transferred data to I/O ports (P1 and P2).


    Original     		PDF H8SX/1663 H8SX/1622 H8SX/1638 H8SX/1648 H8SX/1648A H8SX/1648L H8SX/1648G REJ06B0816-0100/Rev h8sx

    fpga cdma ip vhdl examples

    Abstract: DS792 AMBA AXI4 stream specifications xc6vlx240t XPS Central DMA cdma system implementation fpga cdma by vhdl examples
    Text: LogiCORE IP AXI Central Direct Memory Access v3.02.a DS792 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced eXtensible Interface Central Direct Memory Access (AXI CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx


    Original     		PDF DS792 fpga cdma ip vhdl examples AMBA AXI4 stream specifications xc6vlx240t XPS Central DMA cdma system implementation fpga cdma by vhdl examples

    IVC2 toshiba

    Abstract: C compiler manual toshiba MeP mep toshiba programming MEP-c5 Venezia MEP toshiba C compiler Toshiba MeP MEP core mep integrator MPE toshiba
    Text: C Compiler Mannual for VSDK C Compiler Manual For VSDK Revision 1.7 Sep. 27, 2010 Semiconductor Company MEPUM09004-E17 i C Compiler Mannual for VSDK Preface This manual supplements the explanation of C compiler mentioned in C Compiler Manual below ・C Compiler


    Original     		PDF MEPUM09004-E17 IVC2 toshiba C compiler manual toshiba MeP mep toshiba programming MEP-c5 Venezia MEP toshiba C compiler Toshiba MeP MEP core mep integrator MPE toshiba

    2215S

    Abstract: 0x600000
    Text: APPLICATION NOTE H8S/2200 Series DTC Transfer Software Activation Introduction Transfers data on an SRAM chip to other addresses on the chip by DTC that is activated by software. Target Device H8S/2215 Contents 1. Overview . 2


    Original     		PDF H8S/2200 H8S/2215 REJ06B0348-0100Z/Rev 2215S 0x600000

    DR102

    Abstract: QFP208-P-2828-K4 STD-1149 ot2a OKI Package code
    Text: APPLICATION NOTE O K I A S I C P R O D U C T S JTAG Boundary Scan for 0.8µ m and 0.5µ m SOG and CSA Technologies April 1995 This document was created with FrameMaker 4.0.4 CONTENTS Introduction . 1


    Original     		PDF 1-800-OKI-6388 DR102 QFP208-P-2828-K4 STD-1149 ot2a OKI Package code

    equivalent bc 517

    Abstract: bc 312 equivalent Controller BC 415 MPC561 MPC563 BC2 373 EQUIVALENT BC 309 26vf 3410Z BC 247
    Text: SECTION 25 IEEE 1149.1-COMPLIANT INTERFACE JTAG 25.1 IEEE 1149.1 Test Access Port (TAP) and Joint Test Action Group (JTAG) The chip design includes user-accessible test logic that is compatible with the IEEE 1149.1-1994 Standard Test Access Port and Boundary Scan Architecture. The


    Original     		PDF MPC561/ MPC563 MPC561/MPC563 equivalent bc 517 bc 312 equivalent Controller BC 415 MPC561 MPC563 BC2 373 EQUIVALENT BC 309 26vf 3410Z BC 247

    LB 124 d

    Abstract: BH RV transistor i960 Cx Processor Instruction Set Quick Reference 80960JT 80960RM 80960RN REQ64 BIT3102 273160 80960
    Text: i960 RM/RN I/O Processor Developer’s Manual July 1998 Order Number: 273158-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability


    Original     		PDF 80960RxJx Index-11 LB 124 d BH RV transistor i960 Cx Processor Instruction Set Quick Reference 80960JT 80960RM 80960RN REQ64 BIT3102 273160 80960

    Visconti

    Abstract: save32gpr save64gpr processorspe The PowerPC Architecture A Specification for a New Family of RISC Processors
    Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. E500ABIUG/D 3/2003 Rev. 1.0 PowerPC e500 Application Binary Interface User’s Guide For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc.


    Original     		PDF E500ABIUG/D CH370 64-bit Visconti save32gpr save64gpr processorspe The PowerPC Architecture A Specification for a New Family of RISC Processors

    save32gpr

    Abstract: PowerPC ABI freescale Visconti POWERPC E500 instruction set xe500
    Text: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. E500ABIUG/D 3/2003 Rev. 1.0 PowerPC e500 Application Binary Interface User’s Guide For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. HOW TO REACH US:


    Original     		PDF E500ABIUG/D 64-bit save32gpr PowerPC ABI freescale Visconti POWERPC E500 instruction set xe500

    catv DISTRIBUTION NETWORK diagram

    Abstract: HD6409 mar 4sm SR211 WD2840A RCS3 258 CR01 CR05 CR06 CR10
    Text: ' P . : WESTERN DiC/TAL C O R P O R A T I O N WD2840 Local Network Token Access Controller DNC E Z , ^ 48 Z U v c c + 5V SQ I I I 2 47 WE c z ~CS c z 3 46 Z I I IA0 4 45 Z Z I IA2 RE i n 5 44 Z Z I IA3 C LK i n 6 43 Z D MR d DALO d 7 42 Z Z I V D D ( + 12V)


    OCR Scan     		PDF WD2840 catv DISTRIBUTION NETWORK diagram HD6409 mar 4sm SR211 WD2840A RCS3 258 CR01 CR05 CR06 CR10

    WD2840A

    Abstract: IC JRC 2840 CRC-16-CCIT
    Text: W E S T E R N D /C /T A L C O R P O R A T I O N WD2840 Local Network Token Access Controller DNC d SQ • Broadcast Medium Independent Coax, RF, CATV, IR, etc. • Up to 254 nodes • Dual DMA/Highly efficient Memory Block Chaining • Token based protocol


    OCR Scan     		PDF WD2840 WD2840 WD2840A IC JRC 2840 CRC-16-CCIT

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Cl Am79C82A Advanced Micro Devices CMOS Data Path Controller DPC DISTINCTIVE CHARACTERISTICS • Performs reception and transmission of frames Performs parity check and generation ■ Byte (8 + 1 bits) to word (32 + 4 bits) conversions 145-lead pin grid array package


    OCR Scan     		PDF Am79C82A 145-lead 09730-001B Am79C81 9730-025A CGX145

    14K14D

    Abstract: dpc 050 hex Am79C82 H-14 79C83 AM79C82AGC np dpc 050 AMD Supernet AMD AM79C82A
    Text: a Preliminary Advanced Micro Devices Am79C82A CMOS Data Path Controller DPC DISTINCTIVE CHARACTERISTICS • Performs reception and transmission of frames ■ Byte (8 + 1 bits) to word (32 + 4 bits) conversions ■ Reports error status ■ Performs parity check and generation


    OCR Scan     		PDF Am79C82A 145-lead Am79C81 14433D 02S752? GD32345 PQJ168* 168-Pin 14K14D dpc 050 hex Am79C82 H-14 79C83 AM79C82AGC np dpc 050 AMD Supernet AMD AM79C82A

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Am79C82A Advanced Micro Devices CMOS Data Path Controller DPC DISTINCTIVE CHARACTERISTICS • Performs reception and transmission of frames Performs parity check and generation ■ Byte (8 + 1 bits) to word (32 + 4 bits) conversions 145-lead pin grid array package


    OCR Scan     		PDF Am79C82A 145-lead Am79C8l D0323M3 84-Pin PQR168* 168-Pin 14433D PQJ168*

    t7115a

    Abstract: No abstract text available
    Text: User Manual October 1997 microelectronics group Lucent Technologies Bell Labs Innovations T7115A Synchronous Protocol Data Formatter Description Transparent mode no protocol supports ECMA 102 and ITU-T 1.463 RA2 rate adaption standards This user manual familiarizes the reader with the


    OCR Scan     		PDF T7115A T7115A forT7115A T7115A, T711se 05005b