Untitled
Abstract: No abstract text available
Text: 19-2335; Rev 0; 1/02 Tracking, Sinking and Sourcing, Synchronous Buck Controller for DDR Memory and Termination Supplies Features ♦ 25A Sourcing and Sinking Current ♦ Automatically Sets VTT to 1/2VDDR ♦ VTT and VTTR Within 1% of 1/2VDDR ♦ Smallest Output Capacitors
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MAX1917
MAX1917
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fet 2n7002K
Abstract: transistor 123 DL 2n7002k 2k
Text: 19-2335; Rev 0; 1/02 Tracking, Sinking and Sourcing, Synchronous Buck Controller for DDR Memory and Termination Supplies Features ♦ 25A Sourcing and Sinking Current ♦ Automatically Sets VTT to 1/2VDDR ♦ VTT and VTTR Within 1% of 1/2VDDR ♦ Smallest Output Capacitors
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MAX1917
MAX1917
fet 2n7002K
transistor 123 DL
2n7002k 2k
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LP2994
Abstract: LP2994M LP2994MX M08A
Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
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LP2994
LP2994
LP2994M
LP2994MX
M08A
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LP2994
Abstract: LP2994M LP2994MX M08A
Text: LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
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LP2994
LP2994
CSP-9-111S2)
CSP-9-111S2.
LP2994M
LP2994MX
M08A
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Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
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G2996
G2996
SSTL-18
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power filter 25v
Abstract: G2996 G2996F1UF G2996F1U G2996P1U SSTL-18
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
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G2996
G2996
SSTL-18
power filter 25v
G2996F1UF
G2996F1U
G2996P1U
SSTL-18
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Untitled
Abstract: No abstract text available
Text: LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
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LP2994
LP2994
SNVS202B
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Untitled
Abstract: No abstract text available
Text: Obsolete Device LP2994 LP2994 DDR Termination Regulator Literature Number: SNVS202B March 28, 2011 LP2994 DDR Termination Regulator General Description Features The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications Series Stub Termination Logic for active termination of DDRSDRAM. The device utilizes an internal operational amplifier
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LP2994
LP2994
SNVS202B
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Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
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G2996
G2996
SSTL-18
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Untitled
Abstract: No abstract text available
Text: G2996 Global Mixed-mode Technology Inc. DDR I/II Termination Regulator Features General Description The G2996 is a linear regulator designed to meet the JEDEC SSTL-18 ,SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational
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G2996
G2996
SSTL-18
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G2995
Abstract: G2995F1U G2995P1U
Text: G2995 Global Mixed-mode Technology Inc. DDR Termination Regulator Features General Description The G2995 is a linear regulator designed to meet the JEDEC SSTL-2 and SSTL-3 Series Stub Termination Logic specifications for termination of DDR-SDRAM. It contains a high-speed operational amplifier that provides excellent response to the load transients. This
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G2995
G2995
G2995F1U
G2995P1U
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UR5595L
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
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UR5595
UR5595
QW-R502-062
UR5595L
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UR5595
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM. The device
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UR5595
UR5595
QW-R502-062
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Untitled
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
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UR5595
UR5595
QW-R502-062
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Untitled
Abstract: No abstract text available
Text: UNISONICTECHNOLOGIESCO., LTD UR5595 CMOS IC DDR T ERM I N AT I ON REGU LAT OR ̈ DESCRI PT I ON The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
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UR5595
UR5595
QW-R502-062
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UR5595L
Abstract: UR5595L-SH2-R UR5595 UR5595-S08-R UR5595-SH2-R
Text: UNISONIC TECHNOLOGIES CO., LTD UR5595 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 Stub Series Terminated Logic specifications for termination of DDR-SDRAM.
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UR5595
UR5595
QW-R502-062
UR5595L
UR5595L-SH2-R
UR5595-S08-R
UR5595-SH2-R
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Untitled
Abstract: No abstract text available
Text: Power Capacitors Series/Type: B25834 The following products presented in this data sheet are being withdrawn. Ordering Code B25834L7685K009 B25834L7475K009 B25834L6685K009 Substitute Product Date of Withdrawal 2014-08-14 2014-08-14 2014-08-14 Deadline Last
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B25834
B25834L7685K009
B25834L7475K009
B25834L6685K009
B25834L6475K009
B25834L6106K009
B25834L5686K009
B25834L5685K009
B25834L5156K009
B25834L5106K009
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Untitled
Abstract: No abstract text available
Text: Power Capacitors Series/Type: B25835 The following products presented in this data sheet are being withdrawn. Ordering Code B25835M7474K007 B25835M7224K007 B25835M7104K007 Substitute Product Date of Withdrawal 2014-08-14 2014-08-14 2014-08-14 Deadline Last
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B25835
B25835M7474K007
B25835M7224K007
B25835M7104K007
B25835M6684K007
B25835M6475K007
B25835M6474K007
B25835M6334K007
B25835M6225K007
B25835M6224K007
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northbridge
Abstract: UR5596 UR5596L-S08-R UR5596L-S08-T UR5596-S08-R UR5596-S08-T
Text: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be
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UR5596
UR5596
QW-R502-045
northbridge
UR5596L-S08-R
UR5596L-S08-T
UR5596-S08-R
UR5596-S08-T
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ur5596l
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be
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UR5596
UR5596
QW-R502-045
ur5596l
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Untitled
Abstract: No abstract text available
Text: DDR12 Series | Tracking Dual Output DC/DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25A@2.5V for Vddq supply and 8A@1.25V for Vtt termination Tracking dual output voltages 1.25V @ 8A, 2.5V @ 25A
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DDR12
DDR12-25D08-A
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Untitled
Abstract: No abstract text available
Text: DDR12 Series | Tracking Dual Output DC-DC Converters DDR12 SERIES Dual output High current dual-output power module for DDR memory Single compact module provides 25 A @ 2.5 V for Vddq supply and 8 A @ 1.25 V for Vtt termination Tracking dual output voltages 1.25 V @ 8 A, 2.5 V @ 25 A
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DDR12
DDR12-25D08-AJ
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Untitled
Abstract: No abstract text available
Text: UNISONIC TECHNOLOGIES CO., LTD UR5596 CMOS IC DDR TERMINATION REGULATOR DESCRIPTION The UTC UR5596 is a linear bus termination regulator and designed to meet JEDEC SSTL-2 Stub-Series Terminated Logic specifications for termination of DDR-SDRAM. It also can be
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UR5596
UR5596
QW-R502-045
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4610H-805-201
Abstract: ZO 103 bourns capacitor network
Text: The 800 Series is obsolete, and not recommended for new designs. PL IA NT Features CO M • Optimizes data transmission in ECL *R oH S systems through proper termination between drivers and receivers ■ Minimizes overshoot, undershoot, and ringing while increasing noise immunity
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