Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CAN CONTROLLER WITH APB INTERFACE Search Results

    CAN CONTROLLER WITH APB INTERFACE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67S539FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S141AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S149AFTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    TB67S549FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface Visit Toshiba Electronic Devices & Storage Corporation
    SSM6J808R Toshiba Electronic Devices & Storage Corporation MOSFET, P-ch, -40 V, -7 A, 0.035 Ohm@10V, TSOP6F, AEC-Q101 Visit Toshiba Electronic Devices & Storage Corporation

    CAN CONTROLLER WITH APB INTERFACE Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ps2 keyboard interface in arm7

    Abstract: ARM720T 16C550 AX07PT7202 AMBA APB UART CABGA 8X8
    Text: Mixed-Signal Products AX07PT7202 Product Summary ARM720T Microcontroller with Embedded Peripherals Preliminary Data Sheet December 1, 2003 www.aeroflex.com/ARM7 FEATURES ‰ Debug interface and boundary scan ‰ 32-bit ARM720T core with cache and MMU ‰ 3.3V supply voltage


    Original     		PDF AX07PT7202 ARM720T® 32-bit ARM720T 70MHz 256-pin ps2 keyboard interface in arm7 16C550 AMBA APB UART CABGA 8X8

    APB to I2C interface

    Abstract: i2c controller with apb interface AMBA APB bus protocol vhdl i2c DB-I2C-M-APB complete I2C specifications verilog program for 16 bit processor verilog ARC processor i2c/APB to I2C interface
    Text: Digital Blocks DB-I2C-M-APB Semiconductor IP APB Bus I2C Controller General Description The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface


    Original     		PDF

    i2c controller with apb interface

    Abstract: APB to I2C interface port expander 32-bit i2c CDC16xxF Can controllers can controller with apb interface
    Text: DEVELOPMENT TOOLS Complementary Tools for 16/32-Bit CAN Controllers April/2005 Complementary Tools for 16/32-Bit CAN Controllers For evaluation and early SW development, a set of extension boards is available. The boards have a standard interface and can be used in combination with the Application


    Original     		PDF 16/32-Bit April/2005 16xxF 32xxG. 32xxG 6255-001-1DT D-79108 D-79008 i2c controller with apb interface APB to I2C interface port expander 32-bit i2c CDC16xxF Can controllers can controller with apb interface

    Untitled

    Abstract: No abstract text available
    Text: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal


    Original     		PDF SPEAR-09-H022 ARM926EJ-S PBGA420

    PL050

    Abstract: AMBA APB bus protocol 0143C PS2 keyboard PROTOCOL state machine for axi to apb bridge AMBA AXI verilog code keyboard interfacing controllers code keyboard interfacing with controllers using c PC keyboard CIRCUIT diagram PL05
    Text: ARM PrimeCell PS2 Keyboard/Mouse Interface PL050 Technical Reference Manual Copyright 1999 ARM Limited. All rights reserved. ARM DDI 0143C ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual Copyright © 1999 ARM Limited. All rights reserved.


    Original     		PDF PL050) 0143C PL050 AMBA APB bus protocol 0143C PS2 keyboard PROTOCOL state machine for axi to apb bridge AMBA AXI verilog code keyboard interfacing controllers code keyboard interfacing with controllers using c PC keyboard CIRCUIT diagram PL05

    PL181

    Abstract: AMBA 3.0 technical summary Signal Path Designer e/PL181
    Text: ARM PrimeCell MultiMedia Card Interface PL181 Technical Reference Manual ARM DDI 0205B ARM PrimeCell™ Technical Reference Manual Copyright 2000, 2001 ARM Limited. All rights reserved. Release information Change history Date Issue Change December 2000


    Original     		PDF PL181) 0205B PL181 AMBA 3.0 technical summary Signal Path Designer e/PL181

    PS2 keyboard PROTOCOL

    Abstract: PL050 PL05 ps2 keyboard 0143C ibm ps2 ps2 keyboard interface scan
    Text: ARM PrimeCell PS2 Keyboard/Mouse Interface PL050 Technical Reference Manual DDI 0143C ARM PrimeCell™ PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history


    Original     		PDF PL050) 0143C PS2 keyboard PROTOCOL PL050 PL05 ps2 keyboard 0143C ibm ps2 ps2 keyboard interface scan

    PL180

    Abstract: DDI0172A Secure Digital multimedia PL180 Signal Path Designer Multimedia Card Specification 2.11
    Text: ARM PrimeCell Multimedia Card Interface PL180 Technical Reference Manual Copyright 1998 ARM Limited. All rights reserved. ARM DDI0172A ARM PrimeCell Multimedia Card Interface (PL180) Technical Reference Manual Copyright © 1998 ARM Limited. All rights reserved.


    Original     		PDF PL180) DDI0172A PL180 DDI0172A Secure Digital multimedia PL180 Signal Path Designer Multimedia Card Specification 2.11

    Untitled

    Abstract: No abstract text available
    Text: SPEAR-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC DATA BRIEF Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with 8 channels internal DMA high speed


    Original     		PDF SPEAR-09-H020 ARM926EJ-S PBGA420

    0146C

    Abstract: divide-by-288
    Text: ARM PrimeCell Audio CODEC Interface PL040 Technical Reference Manual ARM DDI 0146C ARM PrimeCell™ Audio CODEC Interface (PL040) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history Description


    Original     		PDF PL040) 0146C 0146C divide-by-288

    ahb to i2c

    Abstract: multiport memory controller
    Text: SPEAr ARM 946, 400K Gates e-ASIC, Large IP Portfolio SoC DATA BRIEF Features • ARM946-ES fMAX = 192MHz ■ 400k equivalent customizable gates ■ AMBA 2.0 compliant Bus fMAX = 96 MHz ■ Clock generator ■ SDRAM, SRAM / FLASH interfaces ■ Ethernet 10/100


    Original     		PDF ARM946-ES 192MHz PBGA568 35x35mm) 35x35 CD00061363 ahb to i2c multiport memory controller

    state machine for axi to apb bridge

    Abstract: state machine diagram for axi bridge AMBA AXI to APB BUS Bridge verilog code state machine for ahb to apb bridge keyboard datasheet keyboard TIMING DIAGRAMS AMBA APB bus protocol keyboard CIRCUIT diagram keyboard interfacing controllers code keyboard interfacing with controllers using c
    Text: AMBA Keyboard/Mouse PS/2 Interface Datasheet Copyright 1996-1998 ARM Limited. All rights reserved. ARM DDI 0096B AMBA Keyboard/Mouse PS/2 Interface Datasheet Copyright © 1996-1998 ARM Limited. All rights reserved. Release Information Change history Date


    Original     		PDF 0096B state machine for axi to apb bridge state machine diagram for axi bridge AMBA AXI to APB BUS Bridge verilog code state machine for ahb to apb bridge keyboard datasheet keyboard TIMING DIAGRAMS AMBA APB bus protocol keyboard CIRCUIT diagram keyboard interfacing controllers code keyboard interfacing with controllers using c

    F200

    Abstract: F400 F600
    Text: Features • • • • • • • Compatible with an Embedded ARM7TDMI Processor Interfaces the ARM7TDMI Core and Atmel 32-bit Peripherals One Wait State Inserted Direct Interface with Peripheral Data Controller Fully Scan Testable up to 98% Fault Coverage


    Original     		PDF 32-bit 1286C F200 F400 F600

    ARM7tdmi pin configuration

    Abstract: AMBA peripheral bus 0xFFF03
    Text: Features Compatible with an Embedded ARM7TDMI Processor Interfaces the ARM7TDMI Core and Atmel 32-bit Peripherals One Wait State Inserted Direct Interface with Peripheral Data Controller Fully Scan Testable up to 98% Fault Coverage Parametrizable Features on Request:


    Original     		PDF 32-bit 05/00/0M ARM7tdmi pin configuration AMBA peripheral bus 0xFFF03

    verilog code for uart apb

    Abstract: V8102 verilog code for apb V8101 v8001 Xtensa ahb wrapper verilog code verilog code for uart ahb V930 M16550APB
    Text: V8102 - Xtensa to AHB Wrapper Interface XWI 10011DF02 Data Sheet_Rev092 Features Functional Overview • Xtensa Read data bus configuration (32/64/128 bits) • Xtensa Write data bus configuration (32/64/128 bits) • AHB buswidth configuration (32/64/128 bits)


    Original     		PDF V8102 10011DF02 Rev092 M16550APB M146818APB V8001 V8002 M8254APB verilog code for uart apb verilog code for apb V8101 Xtensa ahb wrapper verilog code verilog code for uart ahb V930

    AMBA APB bus protocol

    Abstract: PCA82C250T 16Fdata APB VHDL code
    Text: iAP-CAN 16f APB t lian p m co data sheet A AMB Features: • AMBA (APB) compliant Interface • CAN2.0B compliant • 1Mbit/s with > 8MHz clock • 16 transmit buffers • 16 messages deep receive buffer • Message transmission timeout • Advanced message priority handling


    Original     		PDF

    atmel h020

    Abstract: atmel h022 uart baud rate spear AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905
    Text: SPEAR-09-H022 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates


    Original     		PDF SPEAR-09-H022 ARM926EJ-S PBGA420 atmel h020 atmel h022 uart baud rate spear AA13 MAC110 PBGA420 SPEAR-09-H022 Atmel ARM9 ATMEL 0905

    spdif

    Abstract: spdif receiver fifo generator xilinx spartan verilog code for apb AMBA APB bus sample verilog code for memory read spdif input amba apb XC3S500E verilog code for fifo
    Text: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Core o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample


    Original     		PDF 192kHz 98MHz spdif spdif receiver fifo generator xilinx spartan verilog code for apb AMBA APB bus sample verilog code for memory read spdif input amba apb XC3S500E verilog code for fifo

    verilog code for apb

    Abstract: verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb
    Text: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Core o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample


    Original     		PDF 192kHz 98MHz verilog code for apb verilog code for amba apb bus AMBA APB bus spdif input processor bit stream verilog code for amba apb master verilog code for transmitter IEC-60958 spdif input spdif input processor FIFO amba apb

    LCD interface WITH ARM

    Abstract: MOBILE LCD DISPLAY hd44780 LCD 4 20 hd44780 lcd HD44780 hd44780 lcd controller display controller hd44780 LCD hd44780 lcd controller Verilog HD44780 lcd display
    Text: Product Technical Brief Date: 05/2001 picoPACK LCD Display Controller Interface Introduction Architecture The LCD Display Controller Interface is a synthesiz- for display control purposes. The module is part of the Config Registers picoPACK IP series from picoTurbo, Inc.


    Original     		PDF 16/32-bit pT-100, pT-100Ax, pT-110, pT-110Ax, pT-120, LCD interface WITH ARM MOBILE LCD DISPLAY hd44780 LCD 4 20 hd44780 lcd HD44780 hd44780 lcd controller display controller hd44780 LCD hd44780 lcd controller Verilog HD44780 lcd display

    PWM DC-DC ARM

    Abstract: AMBA Peripheral Bus decoder
    Text: ARM PrimeCell DC-DC Converter Interface PL160 Technical Reference Manual ARM DDI 0147D ARM PrimeCell™ DC-DC Converter Interface (PL160) Technical Reference Manual Copyright ARM Limited 1999. All rights reserved. Release information Change history


    Original     		PDF PL160) 0147D PWM DC-DC ARM AMBA Peripheral Bus decoder

    digital clock verilog code

    Abstract: sample verilog code for memory read verilog code for amba apb master verilog code for apb verilog code for amba apb bus verilog code for dma controller synchronous fifo design in verilog verilog code for transmitter dual port ram verilog amba APB verilog
    Text: Conforms to the IEC 60958 International Standard Programmable: supports both Receiver and Transmitter modes SPDIF-APB Data mode capabilities: Digital Audio Interface Megafunction o Supports sample rates from 3kHz to 192kHz with 98MHz SPDIF system clock o 20/24 bits per sample


    Original     		PDF 192kHz 98MHz digital clock verilog code sample verilog code for memory read verilog code for amba apb master verilog code for apb verilog code for amba apb bus verilog code for dma controller synchronous fifo design in verilog verilog code for transmitter dual port ram verilog amba APB verilog

    atmel h020

    Abstract: M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020
    Text: SPEAr-09-H020 SPEAr Head ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC PRELIMINARY DATA Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates with


    Original     		PDF SPEAr-09-H020 ARM926EJ-S atmel h020 M25Pxxx state machine for ahb to apb bridge multiport memory controller A13 cristal ARM926EJ-S electrical ATMEL 0905 INPUT/atmel h020

    atmel h020

    Abstract: atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 ARM926EJ-S MAC110 PBGA420 SPEAR-09-H022
    Text: SPEAR-09-H022 SPEAr Head200 ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC Features • ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and JTAG interfaces ■ 200K customizable equivalent ASIC gates 16K LUT equivalent with 8 channels internal


    Original     		PDF SPEAR-09-H022 Head200 ARM926EJ-S 16-bit atmel h020 atmel h022 atmel 0713 0x16000000 Atmel PART DATE CODE AA13 MAC110 PBGA420 SPEAR-09-H022