UT54ACS164245SEI
Abstract: No abstract text available
Text: UT54ACS164245SEI RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet June 19, 2007 www.aeroflex.com/16BitLogic LOGIC SYMBOL FEATURES • Flexible voltage operation - 5V bus to 3.3V bus; 5V bus to 5V bus - 3.3V bus to 5V bus; 3.3V bus to 3.3V bus
|
Original
|
PDF
|
UT54ACS164245SEI
16-bit
com/16BitLogic
48-lead
UT54ACS164245SEI
|
Untitled
Abstract: No abstract text available
Text: Interrupt controller 16-bit peripheral data bus Peripheral address bus 16-bit internal Y data bus Internal Y address bus Internal X address bus CPU 16-bit internal X data bus 32-bit internal data bus CDB Buffer Internal address bus (CAB) ROM Block Diagram
|
Original
|
PDF
|
16-bit
32-bit
64-bit
|
MCF5307
Abstract: MCF5206
Text: MCF5307 EXTERNAL BUS INTERFACE MCF5307 External Bus Motorola ColdFire 1- 1 MCF5307 EXTERNAL BUS INTERFACE ▼ MCF5307 External Bus Interface – ColdFire® synchronous standard bus interface – 32-bit address bus, 32-bit data bus unmultiplexed – 3-clock basic bus cycle
|
Original
|
PDF
|
MCF5307
MCF5307
32-bit
MCF5206
|
MPC555
Abstract: No abstract text available
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC555
MPC555
|
MPC566
Abstract: MPC565
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC565/MPC566
MPC566
MPC565
|
MPC555
Abstract: No abstract text available
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC555
MPC555
|
mpc556
Abstract: MPC555 inl2u
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC555
MPC556
mpc556
inl2u
|
MPC555
Abstract: MPC556
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC555
MPC556
MPC556
|
MPC561
Abstract: MPC563 motorola 1116
Text: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.
|
Original
|
PDF
|
MPC561/MPC563
MPC561
MPC563
motorola 1116
|
EP201
Abstract: LFX1200B MPC8260 PowerPC 8260
Text: Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.
|
Original
|
PDF
|
EP201
MPC8260
LFX1200B
94Mhz
LFFC20
115Mhz
LFX1200B
PowerPC 8260
|
bus arbitration
Abstract: APA150-STD EP201 MPC8260
Text: Eureka Technology Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.
|
Original
|
PDF
|
EP201
MPC8260
APA150-STD
40Mhz
AX500-3
126Mhz
RT54SX32S-2
61Mhz
bus arbitration
APA150-STD
|
bus arbitration
Abstract: EP201 LFX1200B MPC8260
Text: Eureka Technology Product Summary EP201 PowerPC Bus Master FEATURES • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. • Automatic bus arbitration for address bus and data bus based on internal bus request. • Separate address bus and data bus tenure with individual grant signals.
|
Original
|
PDF
|
EP201
MPC8260
LFX1200B
94Mhz
bus arbitration
LFX1200B
|
WG128128B
Abstract: db3 datasheet POWER SUPPLY for LED DSA0017310 42VLED
Text: WG128128B Graphic type DB0 Data bus line DB1 Data bus line Data bus line DB2 DB3 DB4 Data bus line Data bus line DB5 Data bus line DB6 Data bus line DB7 Data bus line Date / Instruction seiect RS R/W E CS RES VO VDD Date read / write Enable singnal Chip select
|
Original
|
PDF
|
WG128128B
WG128128B
db3 datasheet
POWER SUPPLY
for LED
DSA0017310
42VLED
|
29 bit
Abstract: SH7709
Text: UBC CPG/WDT 16-bit peripheral data bus 1 INTC Peripheral address bus 1 TLB SH3 CPU 32-bit data bus MMU 32-bit virtual address bus MLT RTC TMU CCN BSC SCI CACHE IrDA 16-bit peripheral data bus 2 DMAC Peripheral address bus 2 32-bit data bus 2 29-bit physical address bus 2
|
Original
|
PDF
|
16-bit
32-bit
29-bit
SH7709
29 bit
|
|
|
521A1
Abstract: No abstract text available
Text: Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet March 2009 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus
|
Original
|
PDF
|
UT54ACS164646S
16-bit
com/16bitLogic
521A1
|
UT54ACS164646S
Abstract: No abstract text available
Text: Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet May 17, 2012 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus
|
Original
|
PDF
|
UT54ACS164646S
16-bit
com/16bitLogic
UT54ACS164646S
|
Untitled
Abstract: No abstract text available
Text: Standard Products UT54ACS164646S RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet January 2008 www.aeroflex.com/16bitLogic FEATURES DESCRIPTION Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus
|
Original
|
PDF
|
UT54ACS164646S
16-bit
com/16bitLogic
|
SH7615
Abstract: bus ethernet Hitachi DSA0084
Text: 16-bit internal data bus Internal address bus 16-bit internal data bus Internal address bus 32-bit cache data bus Block Diagram Cache address bus 1.2 CPU Interrupt controller DSP Hitachi user debug interface X-RAM Serial I/O Serial communication interface
|
Original
|
PDF
|
16-bit
32-bit
SH7615
SH7615
bus ethernet
Hitachi DSA0084
|
VII-320
Abstract: MIL-STD-1553A
Text: QQ0 ILC DATA DEVICE CORPORATION«_ BUS-69008/09/18/19/23/24/25/28/29II REAL-TIME SOFTWARE FOR THE BUS-6551711 IDEA CARD FEATURES DESCRIPTION These real-time software libraries, the BUS-69008II, BUS-69009II, BUS-6901811, BUS-6901911, BUS-69023, BUS-69024,
|
OCR Scan
|
PDF
|
BUS-69008/09/18/19/23/24/25/28/29II
BUS-6551711
MIL-STD-1553B
BUS-69009/1911
MIL-STD-1553A
1553B
BUS-6551711.
VII-320
|
Library
Abstract: BUS-65515
Text: BBS BUS-69050 SERIES ILC DATA DEVICE CORPORATIONS_ "C" SOFTWARE LIBRARY TO SUPPORT THE BUS-61553, BUS-61559, BUS-65515, BUS-65522II, -full I BUS-65529, BUS-65531, and BUS-65555 d a ta sheet DESCRIPTION fi\/MLABl-E_ Free software is now available to sup
|
OCR Scan
|
PDF
|
BUS-69050
BUS-61553
BUS61559
BUS-65515,
BUS-6552211,
BUS-65529,
BUS65531,
BUS-65555.
MIL-STD-1553
Library
BUS-65515
|
69051
Abstract: No abstract text available
Text: 000 BUS-69050 SERIES ILC DATA DEVICE CORPORATION_ "C" SOFTWARE LIBRARY TO SUPPORT THE BUS-61553, BUS-61559, BUS-65515, BUS-65522H, Tuo I BUS-65529, BUS-65531, and BUS-65555 DATASHEETftVA t l a b l e _ Features DESCRIPTION Free softw are is now available to sup
|
OCR Scan
|
PDF
|
BUS-69050
BUS-61553,
BUS-61559,
BUS-65515,
BUS-65522H,
BUS-65529,
BUS-65531,
BUS-65555
S-61553
S-65555.
69051
|
bus arbitration
Abstract: uPD70216 UPD70208H
Text: NEC juPD70208H, 70216H 6. BAU BUS ARBITRATION UNIT The BAU perform s bus arbitration am ong bus masters. A list o f bus masters (units w hich can acquire the bus) is shown below. Table 6-1 Bus Masters Bus M aster Bus Cycle CPU Program fetch, data read/write
|
OCR Scan
|
PDF
|
uPD70208H
uPD70216H
V40HL
V50HL-internal
PD70208H,
70216H
V50HL
bus arbitration
uPD70216
|
DM54ALS640AJ
Abstract: DM74ALS DM74ALS640AN DM74ALS640AWM J20A
Text: DM54ALS640A/DM74ALS640A Inverting Octal Bus Transceivers General Description Features These inverting octal bus transceivers are designed for asynchronous two-way communication between data bus ses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level
|
OCR Scan
|
PDF
|
DM54ALS640A/DM74ALS640A
DM54ALS640A
DM74ALS640A
DM54ALS640AJ
DM74ALS
DM74ALS640AN
DM74ALS640AWM
J20A
|
BUS-65518
Abstract: No abstract text available
Text: EJ00 ILC DATA D EV ICE C O R P O R A T IO N !_ BUS-69008/18/23/24/25/28/29/35II REAL-TIME SOFTWARE FOR THE BUS-6551711 IDEA CARD AND BUS-65518 CARD FEATURES DESCRIPTION These real-time software libraries, sup ported by the BUS-69008II, BUS-69009II, BUS-6901811, BUS-6901911, BUS-69023,
|
OCR Scan
|
PDF
|
BUS-69008/18/23/24/25/28/29/35II
BUS-6551711
BUS-65518
BUS-69008II,
BUS-69009II,
BUS-6901811,
BUS-6901911,
BUS-69023,
BUS-69024,
BUS-69025,
|
