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    BMS 13-48 TYPE 28 CLASS 2 Search Results

    BMS 13-48 TYPE 28 CLASS 2 Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H480FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ PHASE input type Visit Toshiba Electronic Devices & Storage Corporation
    TB67H481FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5/ IN input type Visit Toshiba Electronic Devices & Storage Corporation
    TB67S580FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=1.6 Visit Toshiba Electronic Devices & Storage Corporation
    TB67S581FNG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver/Unipolar Type/Vout(V)=50/Iout(A)=2.5 Visit Toshiba Electronic Devices & Storage Corporation
    TB67S589FTG Toshiba Electronic Devices & Storage Corporation Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation

    BMS 13-48 TYPE 28 CLASS 2 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    1669M-96

    Abstract: B9106 en 60721-3-3 1/takamisawa RELAYS jy 110
    Text: The Power in Electrical Safety Main Catalogue Edition 1/2014 BENDER Group Main Catalogue Edition 1/2014 Subject to change! – Bender GmbH & Co. KG, Germany The catalogue and the articles and illustrations which it contains are protected by copyright. Distribution, translation, microfilming and storing in electronic systems, particularly for commercial purposes, are not permitted without prior permission from the author. We accept no liability


    Original     		PDF D-35305 D-35301 807-es 1669M-96 B9106 en 60721-3-3 1/takamisawa RELAYS jy 110

    IRDH275

    Abstract: TBP103005 IRDH575
    Text: TM The Power in Electrical Safety North American Product Catalog, 2013 Edition 1 BENDER Group North American Product Catalog 2013 Edition 1 USA: Bender Inc. 700 Fox Chase Coatesville, PA 19320 Tel. 800.356.4266 / 610.383.9200 Fax 610.383.7100 E mail: info@bender.org


    Original     		PDF ZT1590 ZT1590RS ZT1591 ZT1591RS ZT1594RS NAE4003010 IRDH275 TBP103005 IRDH575

    ADSP2171KS133

    Abstract: ADSP-2172 C1984 80C51 ADSP-2100 ADSP-2101 ADSP-2171 ADSP-2173 HD15 D2322
    Text: a DSP Microcomputer ADSP-2171/ADSP-2172/ADSP-2173 FEATURES 30 ns Instruction Cycle Time 33 MIPS from 16.67 MHz Crystal at 5.0 V 50 ns Instruction Cycle Time (20 MIPS) from 10 MHz Crystal at 3.3 V ADSP-2100 Family Code & Function Compatible with New Instruction Set Enhancements for Bit Manipulation Instructions, Multiplication Instructions, Biased


    Original     		PDF ADSP-2171/ADSP-2172/ADSP-2173 ADSP-2100 ADSP-2172) 16-Bit ADSSP-2171BS-133 128-Lead ADSP-2171KST-104 ADSP2171KS133 ADSP-2172 C1984 80C51 ADSP-2101 ADSP-2171 ADSP-2173 HD15 D2322

    adsp 210xx architecture diagram

    Abstract: ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21062
    Text: a ADSP-21061 SHARC * DSP Microcomputer Family ADSP-21061 Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 MBit) 5.0 Volt Operation Low Power (Idle 16) Mode SUMMARY High-Performance Signal Computer for Speech, Sound, Graphics and Imaging Applications


    Original     		PDF ADSP-21061 ADSP-21061 ADSP-21060 ADSP-21062 32-Bit 40-Bit ADSP-21061KS-133 adsp 210xx architecture diagram ADSP-21000 ADSP-21060 ADSP-21062

    001C

    Abstract: AD1847 ADSP-2100 ADSP-2181 ADSP2183 ADSP-2183
    Text: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions


    Original     		PDF ADSP-2100 ADSP-2183KST-115 ADSP-2183BST-115 ADSP-2183KST-133 ADSP-2183BST-133 ADSP-2183KST-160 ADSP-2183BST-160 ADSP-2183KST-210 128-Lead 001C AD1847 ADSP-2181 ADSP2183 ADSP-2183

    ADSP-21000

    Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O


    Original     		PDF ADSP-2106x ADSP-21062/ADSP-21062L 32-Bit 240-Lead 225-Ball 40-Bit ADSP-21062KS-133 ADSP-21062KS-160 ADSP-21000 ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L tddg

    D2322

    Abstract: ADSP-2100 ADSP2104 ADSP-2104 ADSP-2104L ADSP-2109 eprom 2764 "vector instructions" saturation
    Text: a Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/


    Original     		PDF ADSP-2104/ADSP-2109 16-Bit ADSP-2104KP-80 ADSP-2109KP-80 ADSP-2104LKP-55 ADSP-2109LKP-55 68-Lead D2322 ADSP-2100 ADSP2104 ADSP-2104 ADSP-2104L ADSP-2109 eprom 2764 "vector instructions" saturation

    ADSP 21 XXX Sharc processor

    Abstract: ADSP-21060 reference manual Analog devices marking Information 74 HTC 00 ADSP filter algorithm implementation ADSP-21062KSZ-133 outline of the heat slug for JEDEC SHARC 21060 ADSP-21060 ADSP-21060C
    Text: SHARC Processor SUMMARY KEY FEATURES—PROCESSOR CORE High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch,


    Original     		PDF 1062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 32-bit 240-lead 225-ball SP-240-2 B-225-2 ADSP 21 XXX Sharc processor ADSP-21060 reference manual Analog devices marking Information 74 HTC 00 ADSP filter algorithm implementation ADSP-21062KSZ-133 outline of the heat slug for JEDEC SHARC 21060 ADSP-21060 ADSP-21060C

    ADSP21000

    Abstract: ADSP-21000 ADSP-21060 ADSP-21060C ADSP-21060LC ADSP-21061
    Text: a ADSP-21060 Industrial SHARC DSP Microcomputer Family ADSP-21060C/ADSP-21060LC SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O


    Original     		PDF ADSP-21060 ADSP-21060C/ADSP-21060LC 32-Bit 240-Lead ADSP-21060CZ-133 ADSP-21060CZ-160 ADSP-21060CW-133 ADSP-21060CW-160 ADSP-21060LCW-133 ADSP-21060LCW-160 ADSP21000 ADSP-21000 ADSP-21060C ADSP-21060LC ADSP-21061

    ADSP21XX block diagram

    Abstract: addressing modes in adsp-21xx taa 723 to 99 ADSP-21xx block diagram hip 051 57 marking Dt0 ADSP-2100 HA20 ADSP-2103 ADSP-2105
    Text: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter


    Original     		PDF ADSP-2100 ADSP-21xx 16-Bit ADSP-2111 ADSP-2111) P-68A ADSP-2164KP-40 ADSP-2164BP-40 ADSP-2164KS-40 ADSP-2164BS-40 ADSP21XX block diagram addressing modes in adsp-21xx taa 723 to 99 ADSP-21xx block diagram hip 051 57 marking Dt0 HA20 ADSP-2103 ADSP-2105

    ADSP21XX block diagram

    Abstract: 2103B marking code crystal 3018 bms 14-4 ADSP-2105BPZ-80 adsp21xx ADSP-2101 P68A HA20
    Text: ADSP-2100 Family DSP Microcomputers ADSP-21xx a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter


    Original     		PDF 16-Bit ADSP-2111 sp/adsp-21xx/adsp-2105/processors/product ADSP21XX block diagram 2103B marking code crystal 3018 bms 14-4 ADSP-2105BPZ-80 adsp21xx ADSP-2101 P68A HA20

    ADSP-21000

    Abstract: ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L ADSP-21062CS-160
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21062/ADSP-21062L SUMMARY High Performance Signal Processor for Communications, Graphics and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch and Nonintrusive I/O


    Original     		PDF ADSP-2106x ADSP-21062/ADSP-21062L 32-Bit 240-Lead 40-Bit 2CS-160 ADSP-21062LKS-133 ADSP-21062LKS-160 ADSP-21000 ADSP-21020 ADSP-21060 ADSP-21062 ADSP-21062L ADSP-21062CS-160

    Untitled

    Abstract: No abstract text available
    Text: a Commercial Grade SHARC Family DSP Microcomputer ADSP-21061/ADSP-21061L SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O


    Original     		PDF ADSP-21061/ADSP-21061L 32-bit 240-Lead 225-Ball

    adsp 210xx architecture diagram

    Abstract: ADSP-21060 reference manual ADSP21000 ADSP-21000 ADSP-21060 ADSP-21060L ADSP-21061 ADSP-21062 64 point FFT radix-4
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 32-Bit 240-Lead 40-Bit ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060LKS-133 adsp 210xx architecture diagram ADSP-21060 reference manual ADSP21000 ADSP-21000 ADSP-21060 ADSP-21060L ADSP-21061 ADSP-21062 64 point FFT radix-4

    234 N02

    Abstract: 74 HTC 00 74 HTC 08 SIMULATOR 4...20 mA adsp 210xx architecture diagram TRW a-20 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21061/ADSP-21061L Pin-Compatible with ADSP-21060 4 Mbit and ADSP-21062 (2 Mbit) Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats


    Original     		PDF ADSP-2106x ADSP-21061/ADSP-21061L ADSP-21060 ADSP-21062 40-Bit 32-Bit 80-Bit 234 N02 74 HTC 00 74 HTC 08 SIMULATOR 4...20 mA adsp 210xx architecture diagram TRW a-20 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L

    ADSP-21061LKSZ

    Abstract: sad diode marking b12 RPBA 01 marking c08 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 Marking Code h06
    Text: a Commercial Grade SHARC Family DSP Microcomputer ADSP-21061/ADSP-21061L SUMMARY High performance signal processor for communications, graphics, and imaging applications Super Harvard Architecture Four independent buses for dual data fetch, instruction fetch, and nonintrusive I/O


    Original     		PDF ADSP-21061/ADSP-21061L 32-bit 240-Lead 225-Ball ADSP-21061LKSZ sad diode marking b12 RPBA 01 marking c08 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21061L ADSP-21062 Marking Code h06

    ADSP-21060 simulator program download

    Abstract: ADSP-21060 reference manual ADSP-21060 SIMULATOR 4...20 mA ADSP21060 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation 240-Lead Thermally Enhanced MQFP Package 225 PBGA Package 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats or 32-Bit FixedPoint Data Format


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 240-Lead 32-Bit 40-Bit ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060KB-160 ADSP-21060 simulator program download ADSP-21060 reference manual ADSP-21060 SIMULATOR 4...20 mA ADSP21060 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER ADSP21000 ADSP-21000 ADSP-21060L ADSP-21061

    ADSP-21060

    Abstract: ADSP21000 ADSP-21000 ADSP-21061 ADSP-21062 ADSP-21060 reference manual 74 HTC 08
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 32-Bit 240-Lead 40-Bit ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060LKS-133 ADSP-21060 ADSP21000 ADSP-21000 ADSP-21061 ADSP-21062 ADSP-21060 reference manual 74 HTC 08

    adsp 210xx architecture diagram

    Abstract: ADSP21000 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21060LKS-160 parallel port 25 pin connector
    Text: a ADSP-2106x SHARC DSP Microcomputer Family ADSP-21060/ADSP-21060L SUMMARY High Performance Signal Processor for Communications, Graphics, and Imaging Applications Super Harvard Architecture Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive I/O


    Original     		PDF ADSP-2106x ADSP-21060/ADSP-21060L 32-Bit 240-Lead 40-Bit ADSP-21060KS-133 ADSP-21060KS-160 ADSP-21060LKS-133 adsp 210xx architecture diagram ADSP21000 ADSP-21000 ADSP-21060 ADSP-21061 ADSP-21062 ADSP-21060LKS-160 parallel port 25 pin connector

    00FF

    Abstract: ADSP-21000 ADSP-21020 ADSP-21060 ADSP-21061 ADSP-21062
    Text: ADSP-21061 SHARC Preliminary Data Sheet October 1996 For current information contact Analog Devices at 617 461-3881 ADSP-21060/62 SHARC ADSP-21061 ADSP-21061 Super Harvard SHARC Architecture Computer PreliminaryData Information Preliminary Sheet SUMMARY


    Original     		PDF ADSP-21061 ADSP-21060/62 ADSP-21061 32-Bit ADSP-21061KS-133x ADSP-21061KS-160x C2216 240-lead 00FF ADSP-21000 ADSP-21020 ADSP-21060 ADSP-21062

    transistor smd DAG

    Abstract: marking code NJ SMD Transistor QML-38535 ADSP21060DZ-160 33dt 8X4X32 16X40 MS3157
    Text: REVISIONS LTR DATE DESCRIPTION Editorial changes to table I 8/ and changes to case outlines X and Y. - tmh APPROVED YR-MO-DA 99-11-24 Monica L. Poelking REV SHEET 55 REV SHEET 35 36 37 38 REV 39 40 41 A SHEET 15 16 17 REV STATUS OF SHEETS 18 19 42 43 A 20


    OCR Scan     		PDF AGENCIDW-160/QML transistor smd DAG marking code NJ SMD Transistor QML-38535 ADSP21060DZ-160 33dt 8X4X32 16X40 MS3157

    LSK 331

    Abstract: QML-38534
    Text: REVISIONS LTR DESCRIPTION DATE APPROVED YR-MO-DA A_ Corrections to table 98-03-23_ K. A. Cottonqim B_ Add device type Rav Monnin


    OCR Scan     		PDF

    SB-TSI

    Abstract: ic sj 2038 reset QML-38534 ir020
    Text: REVISIONS LTR DESCRIPTION APPROVED DATE YR-MO-DA REV SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 9 10 11 12 13 14 REV SHEET REV STATUS OF SHEETS REV SHEET PMIC N/A STANDARD M ICRO CIRCUIT


    OCR Scan     		PDF 32-BIT) 14060LB SB-TSI ic sj 2038 reset QML-38534 ir020

    csc 9803

    Abstract: QML-38534 LA4-DA BMS SYSTEM qualification CE7Y
    Text: REVISIONS LTR A DESCRIPTION DATE YR-MO-DA Add device type REV APPROVED 98-12-10_ K. A. Cottonqim A A A A A A A A A A A A A A A A A A A 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 REV A


    OCR Scan     		PDF AD14060LBF/QML-4 5962-9750702HXC AD14060LTF/QML-4 csc 9803 QML-38534 LA4-DA BMS SYSTEM qualification CE7Y