AMCC S2060
Abstract: RX-6 TX-6 h d 2001 BLM31B601S S2060 S2060A S2060B S2060C S2060D VJ0612
Text: DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit
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AMCC S2060
RX-6 TX-6
h d 2001
BLM31B601S
S2060
S2060A
S2060B
S2060C
S2060D
VJ0612
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BLM31b601s
Abstract: BLM11B601SPB OC-24 S3076 BLM11B601S
Text: Part Number S3076 Revision 1.1 - May 18, 2000 S3076 PRELIMINARY APPLICATION NOTE Board Decoupling Guidelines MULTI-RATE SONET/SDH/CLOCK RECOVERY UNIT The S3076 supports clock recovery for the OC-48, OC-24, Gigabit Ethernet, OC-12, or OC-3 data rates. The CAP1/CAP2 capacitor should be 10 µF in series with 56 Ω resistors. Figure 1 illustrates the connections for the
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S3076
S3076
OC-48,
OC-24,
OC-12,
BLM31b601s
BLM11B601SPB
OC-24
BLM11B601S
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7476 counter
Abstract: pin diagram of ttl 7476 7476 PIN DIAGRAM pin diagram of 7476 ttl 7476 datasheets EMR1 7476 ttl datasheets LM393D-SO8 APPLICATION NOTES 7476 st9 technical manual
Text: ST92F150-EMU2 HDS2V2 Emulator User Manual Release 1.1 July 2001 Ref: DOC-ST92F150-EMU2 INSTRUCTIONS FOR USE—WARNING This product is conform to the 89/336/EEC Directive. It complies with the ITE EN55022 standard for EMC emissions and generic 50082-1 1992 edition immunity standards.
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ST92F150-EMU2
DOC-ST92F150-EMU2
89/336/EEC
EN55022
7476 counter
pin diagram of ttl 7476
7476 PIN DIAGRAM
pin diagram of 7476
ttl 7476 datasheets
EMR1
7476 ttl datasheets
LM393D-SO8
APPLICATION NOTES 7476
st9 technical manual
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BLM11B601S
Abstract: blm11b601 BLM11B601SPB BLM31b601s BLM31B601SPB S3033
Text: Part Number S3033 Revision 1.0 - March 14, 2001 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and
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S3033
OC-3/12
S3033
OC-12
BLM31B601SPB
BLM11B601SPB
D274/R483
BLM11B601S
blm11b601
BLM11B601SPB
BLM31b601s
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BLM31B601S
Abstract: S2062 S2067 VJ0612
Text: Part Number S2067 Revision 1.0 - February 28, 2000 S2067 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2067 dual channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure firstpass success in implementing a functional design with optimal signal quality. This document should be used in conjunction with the product device specification. An elementary knowledge of high-speed printed circuit layout
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S2067
S2067
BLM31B601S
S2062
VJ0612
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BLM31B601SPB
Abstract: BLM31b601s S3024
Text: DECOUPLING APPLICATION NOTE DECOUPLING APPLICATION NOTE S3024 S3024 SONET/SDT/ATM S3024 Example The S3024 Clock Recovery Unit CRU contains a stand-alone CRU PLL. The CAP1/CAP2 pins should be connected to a 1.0 µF capacitor in series with 82Ω resistors. Figure 1 illustrates the connections for the S3024
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S3024
S3024
BLM31B601SPB
BLM31b601s
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BLM31B601S
Abstract: S2062 VJ0612 UFC100 S2078
Text: Part Number S2078 Revision 1.0 - February 25, 2000 S2078 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2078 dual channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure firstpass success in implementing a functional design with optimal signal quality. This document should be used in conjunction with the product device specification. An elementary knowledge of high-speed printed circuit layout
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S2078
S2078
BLM31B601S
S2062
VJ0612
UFC100
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BLM31B601S
Abstract: S2076 VJ0612 2S2076
Text: Part Number S2076 Revision 1.0 - March 24, 2000 S2076 APPLICATION NOTE Application Note and Reference Diagrams Introduction This document is intended to assist customers in using AMCC's S2076 quad channel physical layer device. Details concerning application information, circuit design, layout, and component selection are provided to help insure first-pass success in implementing a functional design with optimal signal quality. This document should be
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S2076
S2076
BLM31B601S
VJ0612
2S2076
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BLM31B601SPB
Abstract: S3026 S3026A S3026A-1
Text: DECOUPLING APPLICATION NOTE DECOUPLING APPLICATION NOTE S3026 S3026 SONET/SDT/ATM S3026 Example The S3026 Clock Recovery Unit CRU contains a stand-alone CRU PLL. The CAP1/CAP2 pins should be connected to a 1.0 µF in series with two resistors (see Table 1). Figure 1 illustrates the connections for the
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S3026
S3026
BLM31B601SPB
S3026A
S3026A-1
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E23 SMD Transistor
Abstract: SMD e23 smd transistor E23 TLV5540 BLM31B601SPT smd transistor E33 tlc5560 E30 E30 E33 SOT-23 TLC5510 74AC11004B
Text: TLC5540/TLC5510/TLC5510A/ TLV5540/TLV5510 Evaluation Module User’s Guide 1999 Mixed-Signal Products SLAU007C IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information
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TLC5540/TLC5510/TLC5510A/
V5540/TL
V5510
SLAU007C
E/TLC5510AINSLE/
TLV5540INSLE/TLV5510INSLE
SN74AC573DW
SOIC-20
TL431AID
TLV431AIDBV5,
E23 SMD Transistor
SMD e23
smd transistor E23
TLV5540
BLM31B601SPT
smd transistor E33
tlc5560
E30 E30 E33 SOT-23
TLC5510
74AC11004B
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BLM31b601s
Abstract: VJ0612
Text: Part Number S2072 Revision 1.0 - August 14, 2000 S2072 DECOUPLING APPLICATION NOTE FOUR PORT BYPASS AND REPEATER FOR FC-AL S2072 Decoupling Layout The S2072 Four Port Bypass and Repeater contains a Clock and Data Recovery CDR PLL. The LPF1/LPF2 pins should be connected to a 2.2 µF (X7R Type) capacitor in series with 24 Ω resistors. Figure 1 illustrates the power
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S2072
S2072.
D118/R173
BLM31b601s
VJ0612
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BLM11B601S
Abstract: BLM11B601SPB BLM31B601SPB S3033
Text: Part Number S3033 Revision 1.0 - January 20, 2000 S3033 APPLICATION NOTE Board Decoupling Guidelines SONET/SDH/ATM OC-3/12 Transceiver S3033 Example The S3033 transceiver chip is a fully integrated serialization/deserialization SONET OC-12 622.08 Mbit/s and
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OC-3/12
S3033
OC-12
BLM31B601SPB
BLM11B601SPB
BLM11B601S
BLM11B601SPB
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LTD-PHY-UL3-001
Abstract: No abstract text available
Text: S4803TBI20 Yukon Datasheet Revision 1.8 June 24, 2002 AMCC - PROPRIETARY AND CONFIDENTIAL RESTRICTED DISTRIBUTION NDA REQUIRED DISTRIBUTION AND USE PURSUANT TO APPLICABLE NON-DISCLOSURE AGREEMENTS Part Number - S4803TBI20 Product Brief Revision 1.8 - July 2001
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S4803TBI20
S4803TBI20
STS-48C
OC-48
48Gbit/sec.
STS-48c/
STM-16/AU-416c)
LTD-PHY-UL3-001
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SG-45 diode
Abstract: NFA62R10C223 sg 421 varistor 168t3 NFM46P11C155 DSS306-55 F223Z16 BL01RN1-A62B1 nfa 102 murata IC 7404 NFA41R10C223
Text: This is the PDF file of catalog No.C31E-4. No.C31E4.pdf 99.8.20 On-Board Type DC EMI Suppression Filter (EMIFIL ) EMI SUPPRESSION FILTER Murata Manufacturing Co., Ltd. Cat.No.C31E-4 This is the PDF file of catalog No.C31E-4. No.C31E4.pdf 99.8.20 MURATA entered the suppression filter field at an early
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C31E-4.
C31E4
C31E-4
SG-45 diode
NFA62R10C223
sg 421 varistor
168t3
NFM46P11C155
DSS306-55 F223Z16
BL01RN1-A62B1
nfa 102 murata
IC 7404
NFA41R10C223
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BLM31B601S
Abstract: EV3038 S3038 SJ300 VJ0612 FERRITE E15 SJ-300
Text: SONET/SDH/ATM OC-12 QUAD TRANSCEIVER EVALUATION BOARD SONET/SDH/ATM OC-12 QUAD TRANSCEIVER EVALUATION BOARD EV3038 EV3038 DESCRIPTION The S3038 evaluation board provides a flexible platform for verifying the operation of the S3038 Quad Transceiver interface circuit. This document provides information on the board contents. It should be used in conjunction with the S3038 data sheet, which contains full technical details on the chips operation.
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EV3038
S3038
S3038
BLM31B601S
EV3038
SJ300
VJ0612
FERRITE E15
SJ-300
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S2060A
Abstract: S2060 BLM31B601S S2060B S2060C S2060D VJ0612 23-CORE
Text: DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit
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S2060A
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S2060B
S2060C
S2060D
VJ0612
23-CORE
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SIEMENS capacitor tantalum
Abstract: siemens matsua ceramic filter 63d40
Text: TitlePage - 80A1010_MA001_05 PowerSpan II PowerPC-to-PCI Bus Switch User Manual Document Number: 80A1010_MA001_05 Document Status: Final Release Date: November 2002 This document discusses the features, capabilities, and configuration requirements of the PowerSpan II. It is intended for
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80A1010
SIEMENS capacitor tantalum
siemens matsua ceramic filter
63d40
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t428 motorola
Abstract: compaq 325 63d40 Motorola XHW
Text: TitlePage - 80A1010_MA001_07 PowerSpan II PowerPC-to-PCI Bus Switch User Manual Document Number: 80A1010_MA001_07 Document Status: Final Release Date: April 2003 This document discusses the features, capabilities, and configuration requirements of the PowerSpan II. It is intended for
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80A1010
t428 motorola
compaq 325
63d40
Motorola XHW
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IC 7404
Abstract: BL01RN1A62T5 nfa 102 murata NFM46P11C155 sg 421 varistor Inductive current sensor of measurement PLT09H INDUCTOR CHIP FERRITE BEAD 3216 murata BNX 3 terminal capacitor
Text: This is the PDF file of catalog No.C31E-3. No.C31E3.pdf 98.9.29 On-Board Type DC EMI Suppression Filter (EMIFIL ) EMI SUPPRESSION FILTER Murata Manufacturing Co., Ltd. Cat.No.C31E-3 This is the PDF file of catalog No.C31E-3. No.C31E3.pdf 98.9.29 MURATA entered the suppression filter field at an early
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C31E-3.
C31E3
C31E-3
IC 7404
BL01RN1A62T5
nfa 102 murata
NFM46P11C155
sg 421 varistor
Inductive current sensor of measurement
PLT09H
INDUCTOR CHIP FERRITE BEAD 3216
murata BNX
3 terminal capacitor
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BLM31B601S
Abstract: S2070 S2070A S2070B VJ0612
Text: DEVICE SPECIFICATION FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION FEATURES • • • • • • • • • • • • • 1062 Mbps Fibre Channel line rates 1250 Mbps (Gigabit Ethernet) line rates
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X3T11
10-bit
D49/R77
BLM31B601S
S2070
S2070A
S2070B
VJ0612
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S3050
Abstract: BLM11B601S BLM31B601SPB BLM11B601SPB OC-24
Text: PLL BOARD DECOUPLING GUIDELINES BOARD DECOUPLING GUIDELINES S3050 S3050 MULTI-RATE SONET/SDH/CLOCK RECOVERY UNIT The S3050 supports clock recovery for the OC-48, OC-24, Gigabit Ethernet, OC-12, or OC-3 data rates. The CAP1/CAP2 capacitor should be 22 µF with series 24Ω resistors and 150kΩ resistors to VCC. The figure below
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S3050
OC-48,
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OC-12,
BLM11B601S
BLM31B601SPB
BLM11B601SPB
OC-24
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Untitled
Abstract: No abstract text available
Text: >4 M C C PRELIMINARY DEVICE SPECIFICATION • Switched networks • Data broadcast environments FEATURES • Repeater with parallel monitor function • Proprietary extended backplanes • Selectable parallel input provides local control of serial bit stream
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1062MHz
X3T11
S2075
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n55t
Abstract: No abstract text available
Text: DEVICE SPECIFICATION FEATURES • 1062 MHz Fibre Channel line rates • Half and full VCO output rates • Functionally compliant ANSI X3T11 Fibre Channel Specification • Transmitter incorporating phase-locked loop (PLL) clock synthesis from low speed reference
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X3T11
10-bit
S2070
n55t
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pt 4115 EQUIVALENT
Abstract: No abstract text available
Text: PRELIMINARY DEVICE SPECIFICATION C G IG A B IT ETH ER N ET TR AN SC EIVER FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz Gigabit Ethernet line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit
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S2060
10-bit
S2060
10E-9
pt 4115 EQUIVALENT
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