lxt971
Abstract: pm5350 actel PLL schematic LXT971 SCHEMATIC LXT1000 LXT9763 PowerQUICC high speed connector
Text: Product Brief Axcelerator Evaluation Platform The Axcelerator evaluation platform has been designed to demonstrate the unique capabilities of Actel’s new Axcelerator family of FPGAs. It provides the designers an easy to use hardware platform to evaluate and test various
|
Original
|
RS-232
RJ-45)
lxt971
pm5350
actel PLL schematic
LXT971 SCHEMATIC
LXT1000
LXT9763
PowerQUICC
high speed connector
|
PDF
|
FBGA 896
Abstract: AX125 AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator Family FPGAs
Text: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device
|
Original
|
18-channel
FBGA 896
AX125
AX2000
CS180
IDTQS32X2384
Silicon Sculptor II
Axcelerator Family FPGAs
|
PDF
|
RTAX1000S
Abstract: RTAX2000S CQFP352 RTAX-S jtag pull-up resistor 10K RTAX2000 RTAX-S library RAM EDAC SEU AC173 ACTEL
Text: Application Note AC173 Differences Between RTAX-S/SL and Axcelerator Introduction RTAX-S/SL is Actel's latest FPGA family designed for space applications and is a derivative of the Actel Axcelerator FPGA family. The RTAX-S/SL architecture is based on Actel's multi-featured, high-density AX
|
Original
|
AC173
RTAX1000S
RTAX2000S
CQFP352
RTAX-S
jtag pull-up resistor 10K
RTAX2000
RTAX-S library
RAM EDAC SEU
AC173
ACTEL
|
PDF
|
AX125
Abstract: AX2000 CS180 IDTQS32X2384 Silicon Sculptor II Axcelerator FPGAs Axcelerator Family FPGAs
Text: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device
|
Original
|
18-channel
AX125
AX2000
CS180
IDTQS32X2384
Silicon Sculptor II
Axcelerator FPGAs
Axcelerator Family FPGAs
|
PDF
|
CQFP 256 PIN actel
Abstract: No abstract text available
Text: Axcelerator Family FPGAs Detailed Specifications Operating Conditions Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device
|
Original
|
18-channel
CQFP 256 PIN actel
|
PDF
|
CCGA
Abstract: 896-Pin 624 CCGA AD 149 AE9 FBGA 63 AX125 FBGA 896
Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number
|
Original
|
180-Pin
AX125
IO32NB3F3
IO59NB5F5
CCGA
896-Pin
624 CCGA
AD 149 AE9
FBGA 63
FBGA 896
|
PDF
|
Silicon Sculptor II
Abstract: No abstract text available
Text: Axcelerator Family FPGAs Key Features 350 MHz System/500 MHz Internal Performance 2 Million Equivalent System Gates Up to 339k bits Embedded SRAM with FIFO Logic Flexible Multiple Standard I/Os Innovative 64 bit PerPin FIFO 8 Embedded 1 GHz PLLs Secure Nonvolatile
|
Original
|
System/500
design152
Silicon Sculptor II
|
PDF
|
Untitled
Abstract: No abstract text available
Text: v2 .1 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
700Mb/s
295kbits
|
PDF
|
Untitled
Abstract: No abstract text available
Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
896-Pin
Abstract: smartpower IO290 Axcelerator Family FPGAs
Text: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
MA 6013
Abstract: No abstract text available
Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
RTAX4000S
Abstract: CCGA CG1272 CLGA RTAX-S LG1272 L-34HD-TNR5/7 AC341
Text: Application Note AC341 CCGA to CLGA Adapter Socket Introduction RTAX-S/SL is Actel's next generation, designed-for-space, metal-to-metal antifuse field programmable gate array FPGA family. RTAX-S/SL is a derivative of the Axcelerator family with up to two millionsystem gates. RTAX-S/SL FPGAs provide the designer with nearly 500K ASIC gates and embedded
|
Original
|
AC341
RTAX4000S
CCGA
CG1272
CLGA
RTAX-S
LG1272
L-34HD-TNR5/7
AC341
|
PDF
|
b h21
Abstract: No abstract text available
Text: Revision 18 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
608-bit
b h21
|
PDF
|
AX125
Abstract: AX2000 CQ208 CQ256 FG256 FG324 PQ208 AX2000-CQ256
Text: Revision 17 Axcelerator Family FPGAs Leading-Edge Performance • • • • 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
|
|
CQ352
Abstract: AC342 RTAX-S SK-RT4K-KITTOP RTAX4000S ACTEL FBGA PACKAGE DRAWING
Text: Application Note AC342 CQFP to CLGA Adapter Socket Introduction RTAX-S/L is Actel's next generation, designed-for-space, metal-to-metal antifuse field programmable gate array FPGA family. RTAX-S/L is a derivative of the Axcelerator family with up to two million-system gates. RTAX-S/L FPGAs provide the designer with nearly 500K ASIC gates,
|
Original
|
AC342
CQ352
AC342
RTAX-S
SK-RT4K-KITTOP
RTAX4000S
ACTEL FBGA PACKAGE DRAWING
|
PDF
|
vhdl code for phase frequency detector
Abstract: AC175 vhdl code for PLL
Text: Application Note AC175 Axcelerator Family PLL and Clock Management I n tro du ct i on Where: Clock management is very important in communication and networking applications where low noise and accurate clocks are vital for the design performance. Multiple clock
|
Original
|
AC175
vhdl code for phase frequency detector
AC175
vhdl code for PLL
|
PDF
|
ACTEL CCGA 1152 mechanical
Abstract: AX125 AX2000 CQ208 CQ256 CS180 FG256 PQ208 Trd16 Axcelerator Family FPGAs
Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
ACTEL CCGA 1152 mechanical
Abstract: CS180 antifuse AX125 AX2000 CQ208 CQ256 FG256 PQ208 ACTEL CCGA 624 mechanical
Text: v2.8 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
ACTEL CCGA 1152 mechanical
Abstract: lga 4x4 footprint AX125 AX2000 CQ208 CS180 FG256 PQ208 624-Pin tx 434
Text: v2.7 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
GCLR
Abstract: 676P Axcelerator Family FPGAs
Text: v2.4 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
AF4 din 74
Abstract: AF2.5 din 74 diode t25 4 g8 Axcelerator Family FPGAs
Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
Untitled
Abstract: No abstract text available
Text: v2.5 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
Axcelerator FPGAs
Abstract: AX125 AX2000 CQ208 CS180 PQ208 M33 thermal fuse AK 1022 Axcelerator Family FPGAs
Text: v2 .1 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
700Mb/s
295kbits
Axcelerator FPGAs
AX125
AX2000
CQ208
CS180
PQ208
M33 thermal fuse
AK 1022
Axcelerator Family FPGAs
|
PDF
|
ACTEL CCGA 1152 mechanical
Abstract: ACTEL CCGA 624 mechanical L33 thermal fuse ACTEL CCGA 1152 pin configuration actel PLL schematic footprint cqfp 240 m20 thermal fuse 115 M33 thermal fuse AX125 AX2000
Text: v2.6 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates
|
Original
|
|
PDF
|
