ATLANTIC INTERFACE Search Results

ATLANTIC INTERFACE Result Highlights (5)

Part	Manufacturer	Description
TB67S559FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3 / Clock Interface
TB67S539FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface
TB67S141AFTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Phase Interface
TB67S149AFTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface
TB67S549FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface

ATLANTIC INTERFACE Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Atlantic Interface Abstract: No abstract text available Text: Atlantic Interface January 2001, ver. 1.0 General Description Functional Specification The Atlantic interface allows a consistent interface between all Altera cell and packet MegaCore® functions. The Atlantic interface supports a pointto-point connection. Figure 1 shows examples of the Atlantic interface.	Original	-FS-ATLANTIC-01 Atlantic Interface	PDF
9-Port Fast Ethernet Switch Abstract: 128-PIN PQFP via technologies VT6508 "Spanning Tree" Text: V I A S W I T C H C H I P S VIA Atlantic 8-/9-port Switch Controller Solutions The VIA Atlantic family of switch controllers provides network system manufacturers the ideal platform for building intelligent, cost-effective, and scalable 8-/9-port switches for small to medium sized businesses.	Original	VT6508) VT6509) 9-Port Fast Ethernet Switch 128-PIN PQFP via technologies VT6508 "Spanning Tree"	PDF
Untitled Abstract: No abstract text available Text: Atlantic Interface June 2002, ver. 3.0 Functional Specification 13 Features • ■ ■ ■ ■ ■ ■ Functional Description The direction of data flow on the AtlanticTM interface can be either from master to slave master source or slave to master (slave source).	Original		PDF
Untitled Abstract: No abstract text available Text: Atlantic Interface July 2001, ver. 2.0 Functional Specification 13 Features • ■ ■ ■ ■ ■ ■ Topology Figure 1 shows a block diagram of the AtlanticTM interface, including its control signals. Flexible interface for packet-oriented data of arbitrary length	Original		PDF
ir 7811 Abstract: IMPLOTEC philips 23 Philips 336 TA 2092 N BP317 BYD33J Text: Crop here for Mid-Atlantic paper size DISCRETE SEMICONDUCTORS Fact Sheet 079 High-quality glass-passivated diodes Implotec BYD33J competitor investigation This publication offers a direct comparison between Philips Semiconductors’ glass-passivated BYD33J diode family (based on	Original	BYD33J BYD33J DO-41 ir 7811 IMPLOTEC philips 23 Philips 336 TA 2092 N BP317	PDF
BYV27-200 DO-41 Abstract: philips 23 Philips 336 TA 2092 N BP317 BYV27-200 Text: Crop here for Mid-Atlantic paper size DISCRETE SEMICONDUCTORS Fact Sheet 080 High-quality glass-passivated diodes Glass Bead BYV27-200 competitor investigation This publication offers a direct comparison between Philips Semiconductors’ BYV27-200 Glass Bead diode family and two	Original	BYV27-200 BYV27-200 BYV27-200, DO-41 BYV27-200 DO-41 philips 23 Philips 336 TA 2092 N BP317	PDF
dc motor asa 300f Abstract: 2-digit object counter circuit Simpson ammeter 3344AIXA relay 04501 asa 300f Datasheet-03/dc motor asa 300f 115v 400Hz output 12-pin 4 digits 7-segment led display Digital temperature controller with PT100 rtd Text: C ustomers have counted on Simpson Electric Company to provide quality panel meters for over 70 years. From the analog meter used in Charles Lindbergh’s historic solo trans-Atlantic flight in 1927 to the digital controllers used to raise and lower stages at the 2004 MTV Video Music Awards VMAs show or	Original	RS-485 RS-422 dc motor asa 300f 2-digit object counter circuit Simpson ammeter 3344AIXA relay 04501 asa 300f Datasheet-03/dc motor asa 300f 115v 400Hz output 12-pin 4 digits 7-segment led display Digital temperature controller with PT100 rtd	PDF
IEC-1268 Abstract: 12-pin 4 digits 7-segment led display 3344AIXA analog panel meter adjustable power supply 2 to 36 volt 5amp electronic passive components catalog Wiring Diagram Kwh meter digital asa 300f M135 M235 Text: C ustomers have counted on Simpson Electric Company to provide quality panel meters for over 70 years. From the analog meter used in Charles Lindbergh’s historic solo trans-Atlantic flight in 1927 to the digital controllers used to raise and lower stages at the 2004 MTV Video Music Awards VMAs show or	Original	RS-485 RS-422 IEC-1268 12-pin 4 digits 7-segment led display 3344AIXA analog panel meter adjustable power supply 2 to 36 volt 5amp electronic passive components catalog Wiring Diagram Kwh meter digital asa 300f M135 M235	PDF
IP-CSIX-L1 Abstract: EP1S10F780C5 EP1S10F780C6 EP1S25F1020C6 EP20K400EFC672-1X Text: Common Switch Interface CSIX-L1 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Core Version: 1.0.0 Document Version: 1.0.0 rev1 Document Date: November 2002 Copyright Common Switch Interface (CSIX-L1) MegaCore Function User Guide	Original		PDF
AF200 Abstract: MAC layer sequence number MB250 Text: POS-PHY Level 4 MegaCore Function POSPHY4 August 2001; ver. 1.00 Data Sheet Introduction Optimized for the Altera APEXTM II device architecture, the POS-PHY level 4 MegaCore® function (POSPHY4) interfaces cell and packet transfers between physical (PHY) and link layer devices. The POSPHY4	Original	OC-192, AF200 MAC layer sequence number MB250	PDF
Cyclone II EP2C20F256C7 Abstract: EP2C20F256C7 EP2S30F672C5 TMS320C6000 TMS320C6414T TMS320C6415T TMS320C6416T Text: High-Performance EMIF Bridge Core Application Note 388 September 2005, ver 1.2 Introduction This application note describes the Altera high-performance external memory interface EMIF bridge core. The high-performance EMIF bridge core bridges between an external	Original	TMS320C64x Cyclone II EP2C20F256C7 EP2C20F256C7 EP2S30F672C5 TMS320C6000 TMS320C6414T TMS320C6415T TMS320C6416T	PDF
Xenon 175 Abstract: SFP LVDS altera PC680 PM5392 STM-64 SFP PM3388 PM3392 PM5390 hmzd connector SFP altera Text: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 228 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most	Original	STS-192/STM-64) Xenon 175 SFP LVDS altera PC680 PM5392 STM-64 SFP PM3388 PM3392 PM5390 hmzd connector SFP altera	PDF
sdc 606 Abstract: EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual Text: AN 606: POS-PHY Level 4 SPI-4.2 Loopback Reference Design AN-606-1.0 May 2010 The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2) loopback reference design shows how you can transmit and receive data using the Altera POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III	Original	AN-606-1 sdc 606 EP4GX230KF40C2 EP3SL150F1152C2 hsmc connector altera SOP top marking Stratix II GX FPGA Development Board Reference Manual	PDF
turbo coder pin Abstract: HSDPA VHDL verilog code for parallel turbo vhdl code for turbo EP1S25F780C5 block interleaver in modelsim verilog code for 16 bit ram vhdl code for deserializer HSDPA FPGA verilog hdl code for encoder Text: Turbo Encoder Co-processor Reference Design Application Note AN-317-1.2 Introduction The turbo encoder co-processor reference design is for implemention in an Stratix DSP development board that is connected to a Texas Instruments C6711 DSP Starter Kit DSK . The DSK has a 32-bit external	Original	AN-317-1 C6711 32-bit 16-channel turbo coder pin HSDPA VHDL verilog code for parallel turbo vhdl code for turbo EP1S25F780C5 block interleaver in modelsim verilog code for 16 bit ram vhdl code for deserializer HSDPA FPGA verilog hdl code for encoder	PDF

EP3SE50F780 Abstract: PM3388 EP3C40F780C6 EP4SGX230DF29C3ES EP4SGX70 verilog code for spi4.2 interface altddio_out EP3SE50F Text: POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com MegaCore Version: Document Date: 9.1 November 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
IXP2800 Abstract: IXF1110 Gigabit Logic IXD1110 IXF1010 Gigabit Ethernet MAC SPI AN227 altera board Text: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices May 2003, ver. 1.0 Introduction Application Note 227 The system packet interface level 4–phase 2 SPI-4.2 specification, defined by the Optical Internetworking Forum (OIF), is fast becoming the most	Original	IXF1110 STS-192/STM-64) IXP2800 Gigabit Logic IXD1110 IXF1010 Gigabit Ethernet MAC SPI AN227 altera board	PDF
EP20K30EFC324-1 Abstract: EP20K30EQC208-1 IP-UTOPIA2MS Text: UTOPIA Level 2 Master MegaCore Function 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 2.1.1 2.1.1 rev1 January 2003 UTOPIA Level 2 Master MegaCore Function User Guide Copyright  2003 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all	Original		PDF
PP155 Abstract: No abstract text available Text: PPP Packet Processor 155 Mbps MegaCore Function PP155 August 2001; ver. 1.01 Data Sheet • ■ ■ ■ ■ ■ ■ ■ Features ■ ■ Typical Applications Full-duplex processing capability Octet-synchronous mode operation High-level data link control (HDLC)-type framing	Original	PP155) 32-bit PP155	PDF
TX183 Abstract: No abstract text available Text: POS-PHY Level 4 MegaCore Function v2.1.0 Wrapper Features Application Note 335 January 2004, ver. 1.0 Introduction The Altera POS-PHY Level 4 MegaCore® function provides high-speed cell and packet transfers between physical PHY and link layer devices.	Original		PDF
AN166 Abstract: AN202 fpga frame buffer vhdl examples FIFO buffer threshold YDAT sonet testbench Text: POS-PHY Level 4 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com Core Version: Document Version: Document Date: 1.0.0p4 1.0.0p4 August 2002 Copyright POS-PHY Level 4 MegaCore Function User Guide Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo,	Original	700Mb/s AN166, AN120 OIF2000 AN166 AN202 fpga frame buffer vhdl examples FIFO buffer threshold YDAT sonet testbench	PDF
simple 32 bit LFSR using verilog Abstract: verilog hdl code for traffic light control verilog code 16 bit LFSR cyclic redundancy check verilog source 25.263 SerialLite 8B10B CRC-16 CRC-32 EP1SGX40GF1020C5 Text: SerialLite II MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 9.1 November 2009 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
vhdl code for traffic light control Abstract: vhdl code for crc16 using lfsr verilog code 16 bit LFSR verilog code 8 bit LFSR in scrambler SerialLite verilog code for traffic light control vhdl code 16 bit LFSR with VHDL simulation output testbench of a transmitter in verilog verilog code BIP-8 vhdl code CRC Text: SerialLite II MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other	Original		PDF
PLSM-PP622 Abstract: PP622 STS12CFRM Text: PPP Packet Processor 622 Mbps MegaCore Function PP622 August 2001; ver. 1.01 Data Sheet • ■ ■ ■ ■ ■ ■ ■ Features ■ ■ Typical Applications Full-duplex processing capability Octet-synchronous mode operation High-level data link control (HDLC)-type framing	Original	PP622) 32-bit PLSM-PP622 PP622 STS12CFRM	PDF
fifo vhdl Abstract: POS-PHY pmc OC48 PM5351 PM7325 ep1m20 vhdl code for phy interface Text: POS-PHY Level 2 & 3 Compiler MegaCore Functions April 2001 User Guide v0.5.0 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-POS-PHY_COMP-0.5.0 POS-PHY Level 2 & 3 Compiler MegaCore Functions User Guide Altera, ACEX, APEX, APEX 20K, MegaCore, MegaWizard, Mercury, OpenCore, Quartus and Quartus II are trademarks and/or	Original		PDF

ATLANTIC INTERFACE Search Results

ATLANTIC INTERFACE Result Highlights (5)

ATLANTIC INTERFACE Datasheets Context Search

Atlantic Interface

9-Port Fast Ethernet Switch

Untitled

Untitled

ir 7811

BYV27-200 DO-41

dc motor asa 300f

IEC-1268

IP-CSIX-L1

AF200

Cyclone II EP2C20F256C7

Xenon 175

sdc 606

turbo coder pin

EP3SE50F780

IXP2800

EP20K30EFC324-1

PP155

TX183

AN166

simple 32 bit LFSR using verilog

vhdl code for traffic light control

PLSM-PP622

fifo vhdl