Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    ASSIGNMENT CORE I3 Search Results

    ASSIGNMENT CORE I3 Result Highlights (6)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM3HMFYAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFYADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFYAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HNFZAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HLFZAUG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP64-1010-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM3HPFDADFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1420-0.50-001 Visit Toshiba Electronic Devices & Storage Corporation

    ASSIGNMENT CORE I3 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Untitled

    Abstract: No abstract text available
    Text: Altera Transceiver PHY IP Core User Guide Subscribe Feedback UG-01080 2013.7.1 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents Introduction to the Protocol-Specific and Native Transceiver PHYs.1-1 Protocol-Specific Transceiver


    Original     		PDF UG-01080

    T16E6

    Abstract: fet B20 p03 b09 n03 transistor A09 N03 TRANSISTOR POWER ADSP-BF561SKBCZ5002 ADSP-BF561 t03 package transistor dimension diagram branding F01 B08 REGULATOR
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES 2 internal memory-to-memory DMAs and 1 internal memory DMA controller 12 general-purpose 32-bit timers/counters with PWM capability SPI-compatible port UART with support for IrDA Dual watchdog timers


    Original     		PDF ADSP-BF561 32-bit 256-Ball 297-Ball T16E6 fet B20 p03 b09 n03 transistor A09 N03 TRANSISTOR POWER ADSP-BF561SKBCZ5002 ADSP-BF561 t03 package transistor dimension diagram branding F01 B08 REGULATOR

    fet B20 p03

    Abstract: D04696-0-6 ADSP-BF561SKBCZ5002 MO-192-AAF-1 ADSP-BF561 T16E6
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Two internal memory-to-memory DMAs and one internal memory DMA controller 12 general-purpose 32-bit timers/counters with PWM capability SPI-compatible port UART with support for IrDA® Dual watchdog timers


    Original     		PDF ADSP-BF561 32-bit 256-Ball D04696-0-6/07 BC-256-1 B-297 fet B20 p03 D04696-0-6 ADSP-BF561SKBCZ5002 MO-192-AAF-1 ADSP-BF561 T16E6

    fet B20 p03

    Abstract: T16E6 PF474
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES 2 internal memory-to-memory DMAs and 1 internal memory DMA controller 12 general-purpose 32-bit timers/counters with PWM capability SPI-compatible port UART with support for IrDA Dual watchdog timers


    Original     		PDF ADSP-BF561 16-bit 40-bit 256-ball 297-ball 32-bit forC-256-4 BC-256-4 ADSP-BF561SKBCZ-6V2 fet B20 p03 T16E6 PF474

    Untitled

    Abstract: No abstract text available
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see Memory Architecture on Page 4 Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,


    Original     		PDF ADSP-BF561 16-bit 40-bit 256-ball 297-ball 32-bit

    PF09

    Abstract: HMVIP standard L16 eeprom SRAM-16K ADSP-BF561 DMAC ADSP-BF561SKBZ k08 transistor fet B20 p03 BC2561
    Text: Blackfin Embedded Symmetric Multiprocessor ADSP-BF561 FEATURES Dual symmetric 600 MHz high performance Blackfin cores 328K bytes of on-chip memory see Memory Architecture on Page 4 Each Blackfin core includes Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,


    Original     		PDF ADSP-BF561 16-bit 40-bit 256-ball 297-ball 32-bit PF09 HMVIP standard L16 eeprom SRAM-16K ADSP-BF561 DMAC ADSP-BF561SKBZ k08 transistor fet B20 p03 BC2561

    IXP4XX

    Abstract: ixp425 CP15 IXP420 IXP421 IXP422 pin diagram of intel ixp425 processor Pentium 266 MMX IXP425 ball
    Text: Intel IXP4XX Product Line of Network Processors Datasheet Product Features For a complete list of product features, see “Product Features” on page 9 • ■ ■ ■ ■ ■ ■ ■ Intel® XScale Core Three Network Processor Engines PCI Interface


    Original     		PDF 492-pin IXP4XX ixp425 CP15 IXP420 IXP421 IXP422 pin diagram of intel ixp425 processor Pentium 266 MMX IXP425 ball

    B1566

    Abstract: b1678
    Text: Intel IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet Product Features For a complete list of product features, see “Product Features” on page 9. • ■ ■ ■ ■ ■ ■ ■ Intel XScale® Core Three Network Processor Engines


    Original     		PDF IXC1100 492-pin 400-MHz B1566 b1678

    b1566

    Abstract: b1565 b1566 transistor b1678 B1565 transistor pin diagram of intel ixp425 processor B1677 IXP422 b1565 E B2263
    Text: Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet Product Features For a complete list of product features, see “Product Features” on page 9. • ■ ■ ■ ■ ■ ■ ■ Intel XScale® Core Three Network Processor Engines


    Original     		PDF IXP42X IXC1100 --492-pin 400-MHz b1566 b1565 b1566 transistor b1678 B1565 transistor pin diagram of intel ixp425 processor B1677 IXP422 b1565 E B2263

    B1565

    Abstract: b1566 b1678 IXP422 pin diagram of intel ixp425 processor B1566 equivalent ixp425 KIXDP425BD IXP420 B1680
    Text: Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet Product Features For a complete list of product features, see “Product Features” on page 11. The following features do require The following features do not require


    Original     		PDF IXP42X IXC1100 IXP400 B1565 b1566 b1678 IXP422 pin diagram of intel ixp425 processor B1566 equivalent ixp425 KIXDP425BD IXP420 B1680

    b1566

    Abstract: B1565 B1566 transistor B1565 transistor uart specification b1678 b1677 B1680 ixp425 B1564
    Text: Intel IXP4XX Product Line and IXC1100 Control Plane Processors Datasheet Product Features For a complete list of product features, see “Product Features” on page 9 • ■ ■ ■ ■ ■ ■ ■ Intel® XScale Core Three Network Processor Engines


    Original     		PDF IXC1100 492-pin IXC1100 b1566 B1565 B1566 transistor B1565 transistor uart specification b1678 b1677 B1680 ixp425 B1564

    Untitled

    Abstract: No abstract text available
    Text: 4 Transceiver Configurations in Stratix V Devices 2013.05.06 SV52005 Subscribe Feedback Stratix V devices have a dedicated transceiver physical coding sublayer PCS and physical medium attachment (PMA) circuitry. To implement a protocol, use a PHY IP listed in Table 4-1.


    Original     		PDF SV52005 10GBASE-R 10GBASE-KR

    oki cross

    Abstract: RAMS512X8
    Text: Floorplann.AN Page 1 Friday, October 18, 1996 2:34 PM ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– • Introduction ■


    Original     		PDF

    CSH120

    Abstract: E4000000
    Text: VIP400, VIP410 NRJED311206EN 03/2013 VIP400, VIP410 Electrical Network Protection Reference Manual NRJED311206EN 03/2013 www.schneider-electric.com The information provided in this documentation contains general descriptions and/or technical characteristics of the performance of the products contained herein. This documentation is not intended as a


    Original     		PDF VIP400, VIP410 NRJED311206EN NRJED311206EN VIP410 CSH120 E4000000

    RESERVE_ASDO_AFTER_CONFIGURATION

    Abstract: EP4S100 EP4CE40 EP4CGX15BN11C7 EP4CE6F EP4CGX15BN11 Quartus II Handbook version 9.1 volume Design and EP4CGX15BN11I7 EP4SGX70HF35 EP4CE55
    Text: Quartus II Software Version 9.1 SP2 Release Notes RN-01054-1.0 April 2010 This document provides late-breaking information about the following areas of the Altera Quartus®II software version 9.1 SP2: • “New Features & Enhancements” on page 1 ■ “EDA Interface Information” on page 4


    Original     		PDF RN-01054-1 RESERVE_ASDO_AFTER_CONFIGURATION EP4S100 EP4CE40 EP4CGX15BN11C7 EP4CE6F EP4CGX15BN11 Quartus II Handbook version 9.1 volume Design and EP4CGX15BN11I7 EP4SGX70HF35 EP4CE55

    digital alarm clock vhdl code in modelsim

    Abstract: 8B10B D103 R101 vhdl code for ddr3 altera double data rate megafunction sdc alt_iobuf atom compiles dcfifo modelsim SE 6.3f user guide
    Text: Quartus II Software Release Notes July 2008 Quartus II software version 8.0 Service Pack 1 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your


    Original     		PDF RN-01041-1 digital alarm clock vhdl code in modelsim 8B10B D103 R101 vhdl code for ddr3 altera double data rate megafunction sdc alt_iobuf atom compiles dcfifo modelsim SE 6.3f user guide

    vhdl code for ddr2

    Abstract: EP3C25Q240 EP3C25E144 EP3C5E144 ep3c25f324 alarm clock design of digital VHDL CYCLONE III EP3C25F324 FPGA atom compiles EP3C25F256 altera marking Code Formats Cyclone ii
    Text: Quartus II Software Release Notes July 2007 Quartus II software version 7.1 Service Pack 1 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your


    Original     		PDF RN-01025-1 vhdl code for ddr2 EP3C25Q240 EP3C25E144 EP3C5E144 ep3c25f324 alarm clock design of digital VHDL CYCLONE III EP3C25F324 FPGA atom compiles EP3C25F256 altera marking Code Formats Cyclone ii

    ADSP-21535

    Abstract: No abstract text available
    Text: PRELIMINARY TECHNICAL DATA a ADSP-21535 Preliminary Technical Data SUMMARY 300 MHz High-Performance Blackfin DSP Core Two 16-Bit MACs, Two 40-Bit ALUs, Two 40-Bit Accumulators, Four 8-Bit Video ALUs, and a 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of


    Original     		PDF ADSP-21535 16-Bit 40-Bit 40-Bit 260-Lead B-260) ADSP-21535PKB-300 ADSP-21535PBB-200 ADSP-21535

    EP3C25Q240

    Abstract: CYCLONE III EP3C25F324 FPGA EP3SL110F1152 alt_iobuf Synplicity Synplify Pro 8.8.0.4 10575 CYCLONE 3 ep3c25f324* FPGA EP3C25E144 inkjet module EP3SE80F1152
    Text: Quartus II Software Release Notes May 2007 Quartus II software version 7.1 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your


    Original     		PDF RN-01025-1 EP3C25Q240 CYCLONE III EP3C25F324 FPGA EP3SL110F1152 alt_iobuf Synplicity Synplify Pro 8.8.0.4 10575 CYCLONE 3 ep3c25f324* FPGA EP3C25E144 inkjet module EP3SE80F1152

    ADSP-21535PKB-300

    Abstract: EC38J ADSP-21535 Blackfin dsp 131070
    Text: PRELIMINARY TECHNICAL DATA a ADSP-21535 Preliminary Technical Data SUMMARY 300 MHz High-Performance Blackfin DSP Core Two 16-Bit MACs, Two 40-Bit ALUs, Two 40-Bit Accumulators, Four 8-Bit Video ALUs, and a 40-Bit Shifter RISC-Like Register and Instruction Model for Ease of


    Original     		PDF ADSP-21535 16-Bit 40-Bit 40-Bit 260-Lead B-260) ADSP-21535PKB-300 ADSP-21535PKB-300 EC38J ADSP-21535 Blackfin dsp 131070

    BIOS Writers Guide

    Abstract: E3110 platform environment control interface pentium system software writers manual LGA 1155 Socket PIN diagram wolfdale fsb 1333 peci specification
    Text: Dual-Core Intel Xeon® E3110 Processor Datasheet January 2008 Document Number: 319004-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS


    Original     		PDF E3110 BIOS Writers Guide platform environment control interface pentium system software writers manual LGA 1155 Socket PIN diagram wolfdale fsb 1333 peci specification

    EP4CGX15BN11I7

    Abstract: EP4CE40 EP4CGX15BN11C7 EP4CE30 EP4CE6F RESERVE_ASDO_AFTER_CONFIGURATION EP4CE15 EP4CE10 EP4CGX15BN11 alt4gxb
    Text: Quartus II Software Release Notes RN-01052-1.0 February 2010 This document provides late-breaking information about the following areas of the Altera Quartus®II software version 9.1 SP1. For information about disk space and system requirements, refer to the readme.txt file in your altera/<version number>/quartus directory.


    Original     		PDF RN-01052-1 EP4CGX15BN11I7 EP4CE40 EP4CGX15BN11C7 EP4CE30 EP4CE6F RESERVE_ASDO_AFTER_CONFIGURATION EP4CE15 EP4CE10 EP4CGX15BN11 alt4gxb

    encounter conformal equivalence check user guide

    Abstract: alt_iobuf EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 altera double data rate megafunction sdc
    Text: Quartus II Software Release Notes March 2007 Quartus II software version 7.0 This document provides late-breaking information about the following areas of this version of the Altera Quartus® II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your


    Original     		PDF RN-01023-1 encounter conformal equivalence check user guide alt_iobuf EP3C10 EP3C120 EP3C16 EP3C25 EP3C40 EP3C55 altera double data rate megafunction sdc

    Untitled

    Abstract: No abstract text available
    Text: DALLAS DS4201 USB Audio DAC s e m ic o n d u c to r FEATURES PIN ASSIGNMENT • Fully USB Core Class v 1 .0 Compliant VD Q 1 28 □ NC NC Q 2 27 □ NC NC 3 26 □ NC DGND Q 4 25 □ SUSO • Fully USB Audio Device Class v 1 .0 Com pliant • Com plete Stereo DAC System


    OCR Scan     		PDF