APP550
Abstract: PI40SAX POS-PHY ATM format UB2G5NP OC48 PI40 APP750
Text: Product Description May 2003 UB2G5NP Universal Network Processor Bridge 1 Features • ■ Provides flexible OC48 full-duplex serial backplane interfaces for PI40 fabric chip set PI40X/PI40SAX/ PI20SAX or UB2G5AG aggregation bridge UB2G5NP network processor bridge supports
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PI40X/PI40SAX/
PI20SAX)
APP550)
DS02-389SWCH
APP550
PI40SAX
POS-PHY ATM format
UB2G5NP
OC48
PI40
APP750
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intel 6264
Abstract: APP550 PI40 PI40SAX
Text: Product Description May 2003 UB2G5LC Universal Line Card Bridge 1 Features • ■ Provides flexible full-duplex serial backplane interfaces for UTOPIA level 2 ports to the PI40 fabric chip set PI40X/PI40SAX/PI20SAX or UB2G5AG aggregation bridge. UB2G5LC line card bridge supports (mutually
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PI40X/PI40SAX/PI20SAX)
16-bit
8/16-bit
DS02-390SWCH
intel 6264
APP550
PI40
PI40SAX
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PDF
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APP550
Abstract: Motorola 68030 OC48 PI40 PI40SAX application of microprocessor in traffic signals
Text: Product Description May 2003 UB2G5AG Universal Aggregation Bridge 1 Features 2 Description • Provides flexible OC48 full-duplex aggregation function for up to eight line cards ■ Supports interworking between UB2G5AG, the universal line card bridge UB2G5AG , and the
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APP550)
16-bit,
32-bit
DS02-391SWCH
APP550
Motorola 68030
OC48
PI40
PI40SAX
application of microprocessor in traffic signals
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PDF
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Untitled
Abstract: No abstract text available
Text: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.
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IXF6151
IXF6151
LXT6051
51Mb/s
155Mb/s
GR-253-CORE.
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PDF
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DQ214
Abstract: CY39100V388-200MGC CY7C1370B CYS25G0101DX MPC860 MSM7717-01 XCVE-600 pA2240 prbs parity checker and generator RDAT10
Text: 10, 3610 PRELIMINARY CY7C9536-EVAL POSIC Evaluation Board Introduction Standard MICTOR connectors are used on all buses for external driving and observing signals.This permits the user to directly control all aspects of the board’s operation. Purpose
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CY7C9536-EVAL
CY7C9536-EVAL
DQ214
CY39100V388-200MGC
CY7C1370B
CYS25G0101DX
MPC860
MSM7717-01
XCVE-600
pA2240
prbs parity checker and generator
RDAT10
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PDF
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12697
Abstract: 80MHZ PM7326
Text: PM7326 S/UNI APEX RELEASED APPLICATION NOTE PMC-1991454 ISSUE 2 H/W PROGRAMMER’S GUIDE PM7326 TM S/UNI - APEX S/UNI-APEX ATM/PACKET TRAFFIC MANAGER AND SWITCH HARDWARE PROGRAMMER’S GUIDE RELEASED ISSUE 2: MARCH 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PM7326
PMC-1991454
PM7326
PMC-1981224
12697
80MHZ
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PDF
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MTC27
Abstract: 2x4 TTL demultiplexer 106 35K 045 226 35K AU-AIS Digital Alarm Clock by using ttl MTB 230 P03H GR-253-CORE IXF6151
Text: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.
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IXF6151
IXF6151
LXT6051
51Mb/s
155Mb/s
GR-253-CORE.
MTC27
2x4 TTL demultiplexer
106 35K 045
226 35K
AU-AIS
Digital Alarm Clock by using ttl
MTB 230
P03H
GR-253-CORE
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PDF
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DTC24
Abstract: AU-AIS MTC27 vc-4 digital cross connect 226 35K 2x4 TTL demultiplexer Digital Alarm Clock by ttl Digital Alarm Clock by using ttl P03H GR-253-CORE
Text: IXF6151 28 T1/E1 Mapper Datasheet The IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/ or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface.
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IXF6151
IXF6151
LXT6051
51Mb/s
155Mb/s
GR-253-CORE.
DTC24
AU-AIS
MTC27
vc-4 digital cross connect
226 35K
2x4 TTL demultiplexer
Digital Alarm Clock by ttl
Digital Alarm Clock by using ttl
P03H
GR-253-CORE
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PDF
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processor cross reference
Abstract: TXC-06951-MC telecom bus TXC-06951 VTXP-6
Text: VTXP-6 Device Dual STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 PRODUCT INFORMATION FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.
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TXC-06951
TXC-06951-MC,
TU-11/TU-12/
TEMx28®
06484GG
203-929-8810GG
203-926-9453GG
10/100E
processor cross reference
TXC-06951-MC
telecom bus
TXC-06951
VTXP-6
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PDF
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MTC27
Abstract: 2x4 TTL demultiplexer Pentium MMX 166 Processor MTC13 KLM-1 DTC20 mtc10 VT1536 MTD23 MTD27
Text: Intel IXF6151 28 T1/E1 Mapper Datasheet ® The Intel IXF6151 performs asynchronous mapping and demapping of 28 T1 and/or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus interface. Further
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IXF6151
IXF6151
LXT6051
GR-253-CORE.
MTC27
2x4 TTL demultiplexer
Pentium MMX 166 Processor
MTC13
KLM-1
DTC20
mtc10
VT1536
MTD23
MTD27
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PDF
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2x4 TTL demultiplexer
Abstract: No abstract text available
Text: Intel IXF6151 28 T1/E1 Mapper Datasheet The Intel® IXF6151 28 T1/E1 Mapper performs asynchronous mapping and demapping of 28 T1 and/or E1 PDH signals into SDH or SONET. The PDH side interfaces with T1/E1 LIUs and framers via NRZ Clock and Data, while the SDH/ SONET side uses a standard Telecom bus
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IXF6151
IXF6151
LXT6051
GR-253-CORE.
the41
2x4 TTL demultiplexer
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PDF
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05802
Abstract: txc 270
Text: CUBIT-3 Device Multi-PHY CellBus Access Device TXC-05804 FEATURES DESCRIPTION • Incorporates CellBus switch fabric technology CUBIT-3 is a single-chip solution for implementing lowcost ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are constructed
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TXC-05804
TXC-05802/05802B)
TXC-05810)
8/16-bit)
TXC-05804-MA
05802
txc 270
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PDF
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TXC-05810
Abstract: PHAST-12E TXC-05802B TXC-06212 charge controller using power grid block diagram
Text: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 TECHNICAL OVERVIEW PRODUCT PREVIEW The CUBIT-622 device is a single-chip solution for implementing low-cost ATM multiplexing and switching systems, based on the CellBus architecture. Such
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CUBIT-622
TXC-05805
37-line
8/16-bit)
TXC-05810
PHAST-12E
TXC-05802B
TXC-06212
charge controller using power grid block diagram
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PDF
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TXC-05810
Abstract: TXC-06212 PHAST-12E TXC-05802B
Text: CUBIT-622 Device Multi-PHY CellBus Access Device TXC-05805 DESCRIPTION • 622 Mbit/s performance without multicast • UTOPIA Level 1/2 interface (8/16-bit) with support for 64 ports at 50 MHz • Tandem operation for two devices, supporting dual
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CUBIT-622
TXC-05805
8/16-bit)
TXC-05810
TXC-06212
PHAST-12E
TXC-05802B
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PDF
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T8208
Abstract: PB-01
Text: Product Brief September 2001 CelXpresTM T8208 ATM Interconnect Features • Programmable priority for control/data cells transmission onto cell bus ■ OC-12 data throughput on UTOPIA 16-bit (independently on RX and TX UTOPIA) ■ Microprocessor access to all headers of control
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T8208
OC-12
16-bit)
8-bit/16-bit)
PB01-167DLC
PB01-121DLC)
T8208
PB-01
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PDF
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udf1
Abstract: h9311 i386ex intel CRC-10 bga456 Q67001-H9311 GR-1248-CORE life cycle of sustainable product
Text: ICs for Communications ATM Layer Processor ALP PXB 4350 Version 1.1 Product Overview 04.97 T4350-XV11-O1-7600 PXB 4350 Revision History: Current Version: 04.97 Previous Version: non Page in previous Version Page (in current Version) Editorial Update Subjects (major changes since last revision)
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T4350-XV11-O1-7600
622MBit/s
udf1
h9311
i386ex intel
CRC-10
bga456
Q67001-H9311
GR-1248-CORE
life cycle of sustainable product
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PDF
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T8207
Abstract: application of microprocessor in traffic signals
Text: Product Brief September 2001 CelXpresTM T8207 ATM Interconnect Features • > OC-3 transport capability ■ UTOPIA level 1 and 2 8-bit cell-level handshake interface (ATM or PHY layers) ■ 32 multi-PHY (MPHY) operation ■ Shared UTOPIA mode ■ Egress SDRAM buffer support to expand UTOPIA
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T8207
PB01-166DLC
PB00-117DLC)
T8207
application of microprocessor in traffic signals
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PDF
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spi FIFO
Abstract: IDT88P8344 DSC-6370
Text: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 - Number of errors - Number of bytes FEATURES • • • Functionality - Low speed to high speed SPI exchange device - Logical port LP mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation
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IDT88P8344
800MHz
BH820-1)
88P8344
spi FIFO
IDT88P8344
DSC-6370
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PDF
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Untitled
Abstract: No abstract text available
Text: PRODUCT BRIEF IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4 To request the full IDT88P8344 datasheet, please contact your local IDT Sales Representative or call 1-800-345-7015, you may also email SPI@idt.com FEATURES • • • Functionality - Low speed to high speed SPI exchange device
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IDT88P8344
IDT88P8344
800MHz
BH820-1)
88P8344
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PDF
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GR-1110-CORE
Abstract: I211 951017r1 PM7322
Text: PMC-Sierra, Inc. TECHNICAL OVERVIEW ISSUE 1 PM7322 RCMP ROUTING CONTROL, MONITORING AND POLICING PM7322 RCMP TECHNICAL OVERVIEW Issue 1: October 16, 1995 PMC-Sierra, Inc. 8501 Commerce Court, Burnaby, BC Canada V5A 4N3 604 668 7300 PMC-Sierra, Inc. TECHNICAL OVERVIEW
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PM7322
PM7322
PMC-951017R1
GR-1110-CORE
I211
951017r1
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PDF
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Untitled
Abstract: No abstract text available
Text: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals
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STM-4/OC-12
TXC-06312
VC-4-Xc/STS-1/STS-3c/STC-6c/STS9c/STS-12c
TXC-06312-MB,
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PDF
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load cell
Abstract: No abstract text available
Text: ASPEN Express Device Multi-PHY CellBus Access Device TXC-05806 TECHNICAL OVERVIEW PRODUCT PREVIEW The ASPEN Express device is a single-chip solution for implementing cost-effective ATM multiplexing and switching systems, based on the CellBus architecture. Such systems are
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TXC-05806
8/16-bit)
TXC-05806-MA
load cell
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PDF
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PHAST-12N
Abstract: AU-AIS TXC-06412 MPC8260 MPC860 vc-4 digital cross connect EtherPHAST-48 GR-253-CORE* K1 TXC-06312-MB
Text: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals
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STM-4/OC-12
TXC-06312
VC-4-Xc/STS-1/STS-3c/STC-6c/STS9c/STS-12c
TXC-06312-MB,
PHAST-12N
AU-AIS
TXC-06412
MPC8260
MPC860
vc-4 digital cross connect
EtherPHAST-48
GR-253-CORE* K1
TXC-06312-MB
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PDF
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LTSX E3
Abstract: No abstract text available
Text: DATASHEET PM PMC-981224 ISSUE 3 PRELIMINARY PMC-Sierra, Inc. PM7326 s / u n i -a p e x ATM/PACKET TRAFFIC MANAGER AND SWITCH PM7326 TM S /U N I- APEX S/UNI-APEX ATM/PACKET TRAFFIC MANAGER AND SWITCH DATA SHEET PRELIMINARY ISSUE 3: JUNE 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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OCR Scan
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PMC-981224
PM7326
PM7326
LTSX E3
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PDF
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