LVEL16
Abstract: NBSG16VS practical application of schmitt trigger AND8066D ECL schmitt trigger
Text: AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE STANDARD ECL INTERFACE: DIFFERENTIAL DRIVER AND RECEIVER A typical Emitter Coupled Logic ECL circuit interface
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AND8066/D
r14525
LVEL16
NBSG16VS
practical application of schmitt trigger
AND8066D
ECL schmitt trigger
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practical application of schmitt trigger
Abstract: No abstract text available
Text: AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE STANDARD ECL INTERFACE: DIFFERENTIAL DRIVER AND RECEIVER A typical Emitter Coupled Logic ECL circuit interface
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AND8066/D
r14525
AND8066/D
practical application of schmitt trigger
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LVEL16
Abstract: practical application of schmitt trigger E4-16
Text: AND8066/D Interfacing with ECLinPS Prepared by: Paul Shockman ON Semiconductor Logic Applications Engineering http://onsemi.com APPLICATION NOTE STANDARD ECL INTERFACE: DIFFERENTIAL DRIVER AND RECEIVER A typical Emitter Coupled Logic ECL circuit interface
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AND8066/D
r14525
LVEL16
practical application of schmitt trigger
E4-16
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EP809
Abstract: MC100EP809 MC100EP809FA MC100EP809FAG MC100 SY89809L MC100EP809FAR2 MC100EP809FAR2G
Text: MC100EP809 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into
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MC100EP809
MC100EP809
MC100EP809/D
EP809
MC100EP809FA
MC100EP809FAG
MC100
SY89809L
MC100EP809FAR2
MC100EP809FAR2G
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100EL91
Abstract: MC100EL91 MC100LVEL91
Text: MC100EL91 5 V Triple PECL Input to −5 V ECL Output Translator Description The MC100EL91 is a triple PECL input to ECL output translator. The device receives standard voltage differential PECL signals, determined by the VCC supply level, and translates them to differential
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MC100EL91
MC100EL91
MC100LVEL91.
MC100EL91/D
100EL91
MC100LVEL91
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MC10EP016
Abstract: MC100EP016 MC10E016
Text: MC10EP016, MC100EP016 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter The MC10/100EP016 is a high−speed synchronous, presettable, cascadeable 8−bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family. The counter features internal feedback to TC gated by the TCLD
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MC10EP016,
MC100EP016
MC10/100EP016
MC10E016
MC10EP016/D
MC10EP016
MC100EP016
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KVL11
Abstract: KV11 LVEL11 MC100LVEL11
Text: MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times
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MC100LVEL11
MC100LVEL11
LVEL11
KVL11
MC100LVEL11/D
KVL11
KV11
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EP29
Abstract: MC100EP29 MC10EP29
Text: MC10EP29, MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset http://onsemi.com Description The MC10/100EP29 is a dual master−slave flip−flop. The device features fully differential Data and Clock inputs as well as outputs.
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MC10EP29,
MC100EP29
MC10/100EP29
MC10/100EL29.
MC10EP29/D
EP29
MC100EP29
MC10EP29
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KV05
Abstract: KVL05 MC100EL05 MC100LVEL05 MC100LVEL05MNR4G
Text: MC100LVEL05 3.3V ECL 2-Input Differential AND/NAND Description The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3 V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally
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MC100LVEL05
MC100LVEL05
MC100EL05
LVEL05
MC100LVEL05/D
KV05
KVL05
MC100LVEL05MNR4G
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MC100E416
Abstract: MC10E416 MC10E416FN
Text: MC10E416, MC100E416 5V ECL Quint Differential Line Receiver Description The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0 GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
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MC10E416,
MC100E416
MC10E416/100E416
MC10E416/D
MC100E416
MC10E416
MC10E416FN
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405C
Abstract: 485G NB6L239
Text: NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8
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NB6L239
NB6L239
B2/4/8/16.
NB6L239/D
405C
485G
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LVEP210
Abstract: MC100 MC100EP210 MC100LVEP210
Text: MC100LVEP210 2.5V / 3.3V 1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is
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MC100LVEP210
MC100LVEP210
EP210
LVEP210
MC100LVEP210/D
MC100
MC100EP210
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MC100E171
Abstract: MC10E171 MC10E171FN
Text: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to
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MC10E171,
MC100E171
MC10E/100E171
MC10E171/D
MC100E171
MC10E171
MC10E171FN
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MC100E151
Abstract: MC10E151 MC10E151FN
Text: MC10E151, MC100E151 5V ECL 6-Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 or both go HIGH. The asynchronous
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MC10E151,
MC100E151
MC10E/100E151
MC10E151/D
MC100E151
MC10E151
MC10E151FN
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100EL30
Abstract: MC100EL30 MC100EL30DW
Text: MC100EL30 5V ECL Triple D Flip−Flop with Set and Reset The MC100EL30 is a triple master−slave D flip−flop with differential outputs. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the
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MC100EL30
MC100EL30
MC100EL30/D
100EL30
MC100EL30DW
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MC100H603
Abstract: MC10H603 MC10H603FN MC10H603FNG MC10H603FNR2 plcc socket 68 PLCC bottom view
Text: MC10H603, MC100H603 9−Bit Latch ECL to TTL Translator Description The MC10H/100H603 is a 9−bit, dual supply ECL to TTL translator. Devices in the ON Semiconductor 9−bit translator series utilize the 28−lead PLCC for optimal power pinning, signal flow−through and electrical performance.
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MC10H603,
MC100H603
MC10H/100H603
28-lead
MC10H603/D
MC100H603
MC10H603
MC10H603FN
MC10H603FNG
MC10H603FNR2
plcc socket 68 PLCC bottom view
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2824 footprint dimension
Abstract: MC10EP89 HEP89 HP89 MC10EP89-D 964 dfn8
Text: MC10EP89 3.3V / 5V ECL Coaxial Cable Driver Description The MC10EP89 is a differential fanout gate specifically designed to drive coaxial cables. The device is especially useful in digital video broadcasting applications; for this application, since the system is
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MC10EP89
MC10EP89
MC10EP89/D
2824 footprint dimension
HEP89
HP89
MC10EP89-D
964 dfn8
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KEP16
Abstract: LVEL16 MC100EP16 MC10EP16
Text: MC10EP16, MC100EP16 3.3V / 5V ECL Differential Receiver/Driver Description http://onsemi.com MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 1 8 8 1 Features TSSOP−8 DT SUFFIX CASE 948R • 220 ps Typical Propagation Delay • Maximum Frequency > 4 GHz Typical
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MC10EP16,
MC100EP16
KEP16
HEP16
506AA
MC10EP16/D
KEP16
LVEL16
MC100EP16
MC10EP16
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MC100EP35
Abstract: EL35 HP35 KP35 MC10EP35 code KP35
Text: MC10EP35, MC100EP35 3.3V / 5V ECL JK Flip−Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and
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MC10EP35,
MC100EP35
MC10/100EP35
HEP35
MC10EP35/D
MC100EP35
EL35
HP35
KP35
MC10EP35
code KP35
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KVL51
Abstract: MC100LVEL51 transistor marking PB
Text: MC100LVEL51 3.3V ECL Differential Clock D Flip-Flop Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times
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MC100LVEL51
MC100LVEL51
LVEL51
MC100LVEL51/D
KVL51
transistor marking PB
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E112
Abstract: E212 MC100E112 MC10E112 E212 transistor
Text: MC10E112, MC100E112 5V ECL Quad Driver Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock
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MC10E112,
MC100E112
MC10E/100E112
MC10E/100E111
MC10E112/D
E112
E212
MC100E112
MC10E112
E212 transistor
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100EP
Abstract: EP14 MC100EP14
Text: MC100EP14 3.3V / 5V 1:5 Differential ECL/PECL/HSTL Clock Driver Description The MC100EP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or
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MC100EP14
MC100EP14
LVEP14
MC10EP14/D
100EP
EP14
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Untitled
Abstract: No abstract text available
Text: MC10EP56, MC100EP56 3.3V / 5V ECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are
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MC10EP56,
MC100EP56
MC10/100EP56
MC10EP56/D
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Untitled
Abstract: No abstract text available
Text: MC100EP196B 3.3 V ECL Programmable Delay Chip With FTUNE Descriptions The MC100EP196B is a Programmable Delay Chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar
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MC100EP196B
MC100EP196B
EP195
EP196B
MC100EP196B/D
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