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    bzx 850

    Abstract: bzx 850 30
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18 bzx 850 bzx 850 30 PDF

    CY7C2663KV18

    Abstract: CY7C2665KV18 3M Touch Systems CY7C2663KV18-450BZXC
    Text: CY7C2663KV18, CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2663KV18, CY7C2665KV18 144-Mbit 550-MHz CY7C2663KV18: CY7C2665KV18: CY7C2663KV18 CY7C2665KV18 3M Touch Systems CY7C2663KV18-450BZXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original     		CY7C1568KV18/CY7C1570KV18 72-Mbit CY7C1568KV18 CY7C1570KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features • Separate independent read and write data ports


    Original     		CY7C2642KV18/CY7C2644KV18 144-Mbit 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1643KV18/CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features • Offered in both Pb-free and non Pb-free packages Separate independent read and write data ports


    Original     		CY7C1643KV18/CY7C1645KV18 144-Mbit 450-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features Configurations • 18-Mbit density 1 M x 18, 512 K × 36 CY7C1319KV18 – 1 M × 18 ■ 333-MHz clock for high bandwidth


    Original     		CY7C1319KV18/CY7C1321KV18 18-Mbit CY7C1319KV18 333-MHz CY7C1321KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports


    Original     		CY7C1163KV18/CY7C1165KV18 18-Mbit 550-MHz CY7C1165KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text:  CY7C1143KV18/CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • Separate independent read and write data ports


    Original     		CY7C1143KV18/CY7C1145KV18 18-Mbit 450-MHz CY7C1145KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth


    Original     		CY7C1423KV18/CY7C1424KV18 36-Mbit CY7C1423KV18 CY7C1424KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.0 cycles:


    Original     		CY7C1548KV18/CY7C1550KV18 72-Mbit 450-MHz CY7C1548KV18 CY7C1550KV18 PDF

    CY7C1620KV18-250BZXC

    Abstract: No abstract text available
    Text: CY7C1618KV18, CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18, 8 M × 36 CY7C1618KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth


    Original     		CY7C1618KV18, CY7C1620KV18 144-Mbit CY7C1618KV18 CY7C1620KV18-250BZXC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36)


    Original     		CY7C2168KV18/CY7C2170KV18 18-Mbit 550-MHz CY7C2168KV18 CY7C2170KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1243KV18/CY7C1245KV18 36-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.0 Cycle Read Latency 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		CY7C1243KV18/CY7C1245KV18 36-Mbit CY7C1245KV18 PDF

    CY7C1570KV18

    Abstract: No abstract text available
    Text: CY7C1568KV18/CY7C1570KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36) With Read Cycle Latency of 2.5 cycles:


    Original     		CY7C1568KV18/CY7C1570KV18 72-Mbit CY7C1568KV18 CY7C1570KV18 CY7C1570KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 36-Mbit density (2 M x 18, 1 M × 36)


    Original     		CY7C2268KV18/CY7C2270KV18 36-Mbit CY7C2268KV18 CY7C2270KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1148KV18/CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 18-Mbit density (1 M x 18, 512 K × 36) With Read Cycle Latency of 2.0 cycles:


    Original     		CY7C1148KV18/CY7C1150KV18 18-Mbit 450-MHz CY7C1148KV18 CY7C1150KV18 PDF

    CY7C1470BV33

    Abstract: No abstract text available
    Text: CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit 2 M x 36/4 M × 18/1 M × 72 Pipelined SRAM with NoBL Architecture 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™


    Original     		CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit CY7C1470BV33, CY7C1472BV33, CY7C1474BV33 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18


    Original     		18-Mbit CY7C1312KV18, CY7C1314KV18 CY7C1312KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1518KV18, CY7C1520KV18 72-Mbit DDR II SRAM Two-Word Burst Architecture 72-Mbit DDR II SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18, 2 M × 36 CY7C1518KV18 – 4 M × 18 ■ 333 MHz clock for high bandwidth CY7C1520KV18 – 2 M × 36


    Original     		CY7C1518KV18, CY7C1520KV18 72-Mbit CY7C1518KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1386D CY7C1387D 18-Mbit 512 K x 36/1 M × 18 Pipelined DCD Sync SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined DCD Sync SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades are 200, and 167 MHz ■


    Original     		CY7C1386D CY7C1387D 18-Mbit PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency with ODT 144-Mbit QDR ® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports


    Original     		CY7C2644KV18 144-Mbit 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth


    Original     		CY7C1392KV18 CY7C1393KV18 18-Mbit 333-MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C2568XV18/CY7C2570XV18 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency with ODT 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations • 72-Mbit density (4 M x 18, 2 M × 36)


    Original     		CY7C2568XV18/CY7C2570XV18 72-Mbit CY7C2568XV18 CY7C2570XV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)


    Original     		CY7C1347G 100-pin 119-ball PDF