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    AN1650 Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Type PDF
    AN1650 On Semiconductor Using Wire-OR Ties in ECLInPS Designs Original PDF

    AN1650 Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: AN1650/D Using WireĆOR Ties in ECLinPS Designs http://onsemi.com APPLICATION NOTE This application note discusses the use of wire-OR ties in EClinPS designs. Theoretical Descriptions of the problems associated with wire-OR ties are included as well as an evaluation and SPICE simulation results. In addition, general guidelines


    Original     		PDF AN1650/D r14525

    100EL91

    Abstract: MC100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91
    Text: MC100EL91 3.3V / 5VĄTriple LVPECL / PECL Input to -5V ECL Output Translator The MC100EL91 is a triple LVPECL / PECL input to ECL output translator. The device receives standard or low voltage differential PECL signals, determined by the VCC supply level, and translates them


    Original     		PDF MC100EL91 MC100EL91 MC100LVEL91. r14525 MC100EL91/D 100EL91 MC100EL91DW MC100EL91DWR2 MC100LVEL91

    E212 transistor

    Abstract: E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


    Original     		PDF MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 r14525 MC10E112/D E212 transistor E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 D200-400

    AND8020

    Abstract: EL90 MC100EL90 MC100EL90DW MC100EL90DWR2 100EL90
    Text: MC100EL90 -3.3V / -5VĄTriple ECL Input to PECL Output Translator The MC100EL90 is a triple ECL to PECL translator. The device receives either –3.3 V or –5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL


    Original     		PDF MC100EL90 MC100EL90 r14525 MC100EL90/D AND8020 EL90 MC100EL90DW MC100EL90DWR2 100EL90

    KPT25

    Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
    Text: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal


    Original     		PDF MC100EPT25 MC100EPT25 EPT25 r14525 MC100EPT25/D KPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw

    LQFP32

    Abstract: LQFP-32 MC100 MC100EPT622 MC100EPT622FA MC100EPT622FAR2
    Text: MC100EPT622 3.3V LVTTL/LVCMOS to LVPECL Translator The MC100EPT622 is a 10- Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The device has an OR- ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs


    Original     		PDF MC100EPT622 MC100EPT622 MC100 EPT622 LQFP-32 r14525 MC100EPT622/D LQFP32 LQFP-32 MC100 MC100EPT622FA MC100EPT622FAR2

    marking CODE D2B

    Abstract: MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND
    Text: MC10E104, MC100E104 5VĄECL Quint 2ĆInput AND/NAND Gate The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be


    Original     		PDF MC10E104, MC100E104 MC10E/100E104 MC10E104FN EIA/JESD78 r14525 MC10E104/D marking CODE D2B MC100E104 MC100E104FN MC100E104FNR2 MC10E104 MC10E104FN MC10E104FNR2 marking D3B ECL IC NAND

    KVT23

    Abstract: MC100LVELT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT
    Text: MC100LVELT23 3.3V Dual Differential LVPECL to LVTTL Translator The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL Positive ECL levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which


    Original     		PDF MC100LVELT23 MC100LVELT23 LVELT23 MC100LVELT23/D KVT23 MC100LVELT23D MC100LVELT23DR2 MC100LVELT23DT

    MC100EP90

    Abstract: MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2
    Text: MC10EP90, MC100EP90 -3.3V / -5VĄTriple ECL Input to LVPECL/PECL Output Translator The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals.


    Original     		PDF MC10EP90, MC100EP90 MC10/100EP90 r14525 MC10EP90/D MC100EP90 MC100EP90DT MC100EP90DTR2 MC10EP90 MC10EP90DT MC10EP90DTR2

    MC100E116

    Abstract: MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116
    Text: MC10E116, MC100E116 5VĄECL Quint Differential Line Receiver The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest.


    Original     		PDF MC10E116, MC100E116 MC10E/100E116 r14525 MC10E116/D MC100E116 MC100E116FN MC100E116FNR2 MC10E116 MC10E116FN MC10E116FNR2 E116

    MC100LVEL01

    Abstract: MC100LVEL01D 1085 SPICE model
    Text: MC100LVEL01 3.3VĄECL 4-Input OR/NOR The MC100LVEL01 is a 4–input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a 3.3 V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in


    Original     		PDF MC100LVEL01 MC100LVEL01 LVEL01 KVL01 r14525 MC100LVEL01/D MC100LVEL01D 1085 SPICE model

    KEL04

    Abstract: HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04
    Text: MC10EL04, MC100EL04 5VĄECL 2ĆInput AND/NAND The MC10EL/100EL04 is a 2-input AND/NAND gate. The device is functionally equivalent to the E104 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E104, the EL04 is ideally suited for those


    Original     		PDF MC10EL04, MC100EL04 MC10EL/100EL04 AND8003/D r14525 MC10EL04/D KEL04 HL04 HEL04 e104 MC100EL04 MC10EL04 HL-04

    N100

    Abstract: NB100LVEP17 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24
    Text: NB100LVEP17 2.5V / 3.3V / 5V ECL Quad Differential Driver/Receiver The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.


    Original     		PDF NB100LVEP17 NB100LVEP17 r14525 NB100LVEP17/D N100 NB100LVEP17DT NB100LVEP17DTR2 NB100LVEP17MN TSSOP-20 qfn24 socket N100 transistor QFN-24

    KEP05

    Abstract: HEP05 MC100EP05 MC10EP05
    Text: MC10EP05, MC100EP05 3.3V / 5VĄECL 2-Input Differential AND/NAND The MC10/100EP05 is a 2–input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance


    Original     		PDF MC10EP05, MC100EP05 MC10/100EP05 LVEL05 LVEL05 r14525 MC10EP05/D KEP05 HEP05 MC100EP05 MC10EP05

    MC100E163

    Abstract: MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2
    Text: MC10E163, MC100E163 5VĄECL 2ĆBit 8:1 Multiplexer The MC10E/100E163 contains two 8:1 multiplexers with differential outputs and common select inputs. The select inputs SEL0, 1, 2 control which one of the eight data inputs (A0 – A7, B0 – B7) is propagated to the output.


    Original     		PDF MC10E163, MC100E163 MC10E/100E163 MC10E163FN EIA/JESD78 r14525 MC10E163/D MC100E163 MC100E163FN MC100E163FNR2 MC10E163 MC10E163FN MC10E163FNR2

    MC100EL59

    Abstract: MC100EL59DW MC100EL59DWR2 AND8020
    Text: MC100EL59 5VĄECL Triple 2:1 Multiplexer The MC100EL59 is a triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random


    Original     		PDF MC100EL59 MC100EL59 r14525 MC100EL59/D MC100EL59DW MC100EL59DWR2 AND8020

    E211

    Abstract: MC100E211 MC100E211FN MC100E211FNR2 MC10E211 MC10E211FN MC10E211FNR2 marking code 2b
    Text: MC10E211, MC100E211 5VĄECL 1:6 Differential Clock Distribution Chip The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed


    Original     		PDF MC10E211, MC100E211 MC10E/100E211 r14525 MC10E211/D E211 MC100E211 MC100E211FN MC100E211FNR2 MC10E211 MC10E211FN MC10E211FNR2 marking code 2b

    HEP58

    Abstract: MC100EP58 MC10EP58
    Text: MC10EP58, MC100EP58 3.3V / 5VĄECL 2:1 Multiplexer The MC10/100EP58 is a 2:1 multiplexer. The device is pin and functionally equivalent to the EL58 and LVEL58 devices. The 100 Series contains temperature compensation. • 310 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical


    Original     		PDF MC10EP58, MC100EP58 MC10/100EP58 LVEL58 HEP58 KEP58 r14525 MC10EP58/D HEP58 MC100EP58 MC10EP58

    MC100E154

    Abstract: MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2
    Text: MC10E154, MC100E154 5VĄECL 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables LEN1, LEN2 are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on


    Original     		PDF MC10E154, MC100E154 MC10E/100E154 MC10E154FN r14525 MC10E154/D MC100E154 MC100E154FN MC100E154FNR2 MC10E154 MC10E154FN MC10E154FNR2

    KEL07

    Abstract: HL-07 E107 MC100EL07 MC10EL07 hl07 IC HEL07
    Text: MC10EL07, MC100EL07 5VĄECL 2ĆInput XOR/XNOR The MC10EL/100EL07 is a 2-input XOR/XNOR gate. The device is functionally equivalent to the E107 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E107, the EL07 is ideally suited for those


    Original     		PDF MC10EL07, MC100EL07 MC10EL/100EL07 AND8003/D r14525 MC10EL07/D KEL07 HL-07 E107 MC100EL07 MC10EL07 hl07 IC HEL07

    EL12

    Abstract: MC100LVEL12 MC100LVEL12D
    Text: MC100LVEL12 3.3VĄECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.


    Original     		PDF MC100LVEL12 MC100LVEL12 LVEL12 KVL12it r14525 MC100LVEL12/D EL12 MC100LVEL12D

    transistor BD 889

    Abstract: MC10E1651 MC10E1651FN MC10E1651FNR2 MC10E1651L
    Text: MC10E1651 5V, -5VĄECL Dual ECL Output Comparator with Latch The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC IIIt process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic


    Original     		PDF MC10E1651 MC10E1651 16-pin 20-pin r14525 MC10E1651/D transistor BD 889 MC10E1651FN MC10E1651FNR2 MC10E1651L

    100EL56

    Abstract: MC100EL56 MC100EL56DW MC100EL56DWR2
    Text: MC100EL56 5V ECL Dual Differential 2:1 Multiplexer The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided to ease AC coupling input signals.


    Original     		PDF MC100EL56 MC100EL56 MC100EL56/D 100EL56 MC100EL56DW MC100EL56DWR2

    MC100

    Abstract: MC100E016 MC100EP016 MC100EP016A MC100EP016AFA MC100EP016AFAR2 25pe16
    Text: MC100EP016A 3.3 VĄECL 8-Bit Synchronous Binary Up Counter The MC100EP016A is a high–speed synchronous, presettable, cascadeable 8–bit binary counter. Architecture and operation are the same as the ECLinPS family MC100E016 with higher operating speed.


    Original     		PDF MC100EP016A MC100EP016A MC100E016 r14525 MC100EP016A/D MC100 MC100EP016 MC100EP016AFA MC100EP016AFAR2 25pe16