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    ALTERA CLASSIC EPLDS Search Results

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    epf8282 block

    Abstract: EMP7032 EPM5032A EPM7032V d4454 A7205 EPF8282 84 PLCC pin configuration epc1213 pdf epf8282
    Text: MAX+PLUS II Selection Guide March 1995, ver. 2 Development Systems & Migration Products Altera offers a variety of system configurations and migration products for MAX+PLUS II. MAX+PLUS II supports Altera’s FLEX 10K, FLEX 8000, MAX 9000, MAX 7000, FLASHlogic, MAX 5000, and Classic


    Original     		PDF EPM7192E EPM7128E EPM7160E EPM7256E 160-Pin 192-Pin epf8282 block EMP7032 EPM5032A EPM7032V d4454 A7205 EPF8282 84 PLCC pin configuration epc1213 pdf epf8282

    P5AC312-25

    Abstract: D5AC312-25 D5AC312 N5AC324 p5ac312 N5AC312 P5AC312-30 D5AC32430 EP312DC-25 EP312PC-25
    Text: April 1995, ver. 1 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description Altera Corporation A-DS-312/324.01 EP312 & EP324 Classic EPLDs High-performance EPLDs with 12 macrocells EP312 or 24 macrocells (EP324)


    Original     		PDF -DS-312/324 EP312 EP324 EP312) EP324) 20-pin P5AC312-25 D5AC312-25 D5AC312 N5AC324 p5ac312 N5AC312 P5AC312-30 D5AC32430 EP312DC-25 EP312PC-25

    PAL16L8 programming specifications

    Abstract: P85C220-10 PAL20L8 programming specifications PAL20L8 Altera EP220 N85C220 PAL16L8 GAL20V8B Intel N85C224 ADS-220
    Text: May 1995, ver. 1 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description Altera Corporation A-ds-220/224-01 EP220 & EP224 Classic EPLDs High-performance, low-power Erasable Programmable Logic Devices EPLDs with 8 macrocells


    Original     		PDF -ds-220/224-01 EP220 EP224 16V8/20V8 EP220, EP224; EP220 PAL16L8 programming specifications P85C220-10 PAL20L8 programming specifications PAL20L8 Altera EP220 N85C220 PAL16L8 GAL20V8B Intel N85C224 ADS-220

    Untitled

    Abstract: No abstract text available
    Text: Classic EPLD Family January 1998, ver. 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements


    Original     		PDF

    EP910dm

    Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
    Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements


    Original     		PDF EP610LC-15 EP610LC-25 EP610ILI-12 EP610PC-15 EP610PI-30 EP910dm EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15

    ep600i

    Abstract: EP1800I EP610ILI-12 altera ep610 altera EP1810 EP1800 altera ep900i
    Text: Classic EPLD Family June 1996, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of up to 900 usable gates see Table 1 Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements


    Original     		PDF

    ALTERA MAX 5000 programming

    Abstract: Altera Classic EPLDs Altera Programming Hardware advantages of multipliers Reed-Solomon CODEC an7112 Reed-Solomon altera ALTERA MAX 5000 applications altera flex 8000
    Text: Contents July 1997 Contents by Topic FLEX 10K Devices FLEX 10K Embedded Programmable Logic Family Data Sheet FLEX 10K Embedded Programmable Logic Family Data Sheet Supplement ClockLock & ClockBoost in FLEX 10K Devices Data Sheet Supplement EPF10K50V Embedded Programmable Logic Device Data Sheet Supplement


    Original     		PDF EPF10K50V EPF10K130V 000-Gate EPF10K100 7000S ALTERA MAX 5000 programming Altera Classic EPLDs Altera Programming Hardware advantages of multipliers Reed-Solomon CODEC an7112 Reed-Solomon altera ALTERA MAX 5000 applications altera flex 8000

    ep910 programmer

    Abstract: EP610 programmer EPLD EP610-25 EP1810 EP610-15 EP610-20 EP610-30 EP910 K925
    Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements


    Original     		PDF

    ep910 programmer

    Abstract: EP610 EP610-15 48-macrocell EP1810 EP610-20 EP610-25 EP610-30 EP910 ep610 application
    Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements


    Original     		PDF

    EP600IPC-45

    Abstract: 5962-8686401la ep600i Altera Classic EPLDs altera ep610
    Text: ANbi^n^ EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □


    OCR Scan     		PDF EP600I 5C060 16-macrocell EP610 EP600IPC-45 5962-8686401la ep600i Altera Classic EPLDs altera ep610

    sts37e

    Abstract: EP600IPC-45 EP600IDC-45 EP600IPC-55 altera ep610 5c060 EP600IDM883B55 ep600ilc ep600i EP600IDC45
    Text: EP600I Classic EPLD Data Sheet Supplement March 1995, ver. 2 This data sheet supplement should be used together with the Classic Family Data Sheet and the Altera Device Package Outlines Data Sheet in the current data book. Features ^ □ □ □ □ □ Formerly Intel's 5C060 device


    OCR Scan     		PDF EP600I 5C060 16-macrocell EP610 STS37E EP600IPC-45 EP600IDC-45 EP600IPC-55 altera ep610 EP600IDM883B55 ep600ilc EP600IDC45

    altera EP910

    Abstract: No abstract text available
    Text: ALTERA böE CORP Features Preliminary information □ □ □ □ □ □ □ ì> GS*ìS372 □□□34D1 SÔ7 AL T Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz Pipelined data rates up to 125 MHz


    OCR Scan     		PDF 24-macrocell EP910 EP910T 44-pin EP910A1/O EP910A EP910A-10, EP910A-12, EP910A-15 altera EP910

    TD 265 N 600 KOC

    Abstract: core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S
    Text: 1996 Data Book Data Book June 1996 A-DB-0696-01 Altera, MAX, M A X+PLUS, FLEX, FLEX 10K, FLEX 8000, FLEX 8000A, MAX 9000, MAX 7000, MAX 7000E, MAX 7000S, FLASHlogic, MAX 5000, Classic, M AX+PLUS II, PL-ASAP2, PLDshell Plus, FastTrack, AHDL, MPLD, Turbo Bit, BitBlaster, PENGN, RIPP 10, PLS-ES, ClockLock, ClockBoost,


    OCR Scan     		PDF -DB-0696-01 7000E, 7000S, EPF10K100, EPF10K70, EPF10K50, EPF10K40, EPF10K30, EPF10K20, EPF10K10, TD 265 N 600 KOC core i5 520 Scans-049 camtex trays sii Product Catalog EPM9560 film hot BT 342 project TIL Display 7160S

    PAL20L8

    Abstract: Altera EP220 EP220LC-12 PAL20L8 programming specifications PAL16L8 programming specifications N85C220 Altera 1995 DATE CODE PAL20L8 EP224LC-7 P85C224-80
    Text: Æ onf^ EP220 & EP224 Classic EPLDs Data Sheet May 1995, ver. 1 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description High-performance, low-power Erasable Programmable Logic Devices EPLDs w ith 8 macrocells Combinatorial speeds as low as 7.5 ns


    OCR Scan     		PDF EP220 EP224 16V8/20V8 EP220 EP224; D5T5372 PAL20L8 Altera EP220 EP220LC-12 PAL20L8 programming specifications PAL16L8 programming specifications N85C220 Altera 1995 DATE CODE PAL20L8 EP224LC-7 P85C224-80

    half adder ic

    Abstract: ic number of half adder half adder ic number EP3123 D5AC32430 D5AC324 D5AC312-25
    Text: EP312 & EP324 Classic EPLDs A p ril 19 95, ver. 1 Features D ata S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ General Description High-performance EPLDs with 12 macrocells EP312 or 24 macrocells (EP324) Combinatorial speeds as fast as 25 ns


    OCR Scan     		PDF EP312 EP324 EP312) EP324) 20-pin 0DQ5543 half adder ic ic number of half adder half adder ic number EP3123 D5AC32430 D5AC324 D5AC312-25

    D5AC32430

    Abstract: D5AC312-30 D5AC312
    Text: F e a tu re s G e Pie r a I . D e S C ri p t i o n Altera Corporation A-DS-312/324.01 High-performance EPLDs w ith 12 macrocells EP312 or 24 macrocells (EP324) - Combinatorial speeds as fast as 25 ns - Counter frequencies of up to 33.3 MHz - Pipelined data rates of up to 66 MHz


    OCR Scan     		PDF EP312) EP324) 20-pin EP312 D5AC32430 D5AC312-30 D5AC312

    Altera Classic

    Abstract: No abstract text available
    Text: Classic EPLDs A High-Speed, Low-Power Integration Solution EP1810, tpp = 20 ns 48 W • ë CÖ 24 - A EP910, tpD = 25 ns </ A EP610, tPD= 15 ns 16 8 - Classic EPLDs I EP330, tPD= 12 ns I ~ i— I- r~ 18 22 38 64 U ser I/O Classic EPLDs provide tPDas low as 12 ns


    OCR Scan     		PDF EP1810, EP910, EP610, EP330, EP1810 Altera Classic

    EP610

    Abstract: Altera September 1991 EP610-20 acht30
    Text: altera M7E D corp 05^5375 ODDgPbb T lg W ALT EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ □ □ General Description H igh-density replacem ent for TTL and 74HC w ith up to 600 gates


    OCR Scan     		PDF EP610 16-Macrocell EP630-20 EP630-15, EP630-20 EP630 Altera September 1991 EP610-20 acht30

    program EPM5032

    Abstract: ACCEL Technologies epm5032 Valid Logic Systems
    Text: 1 /Â \l u /A ^ September 1991, ver. 3 In tro d u c tio n *-1 “ V Ï\ Third-Party Development & Programming Support Data Sheet Altera re cognizes the im portance of third-party s u p p o rt tools and w orks closely with m any third-party vend ors to ensure high-quality s upp ort for


    OCR Scan     		PDF

    truth table for ic 74138

    Abstract: 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table
    Text: PLCAD-SUPREME & PLS-SUPREME A+PLUS Programmable Logic Development System & Software Data Sheet September 1991, ver. 1 Features J J J J □ □ H igh-level su p p o rt for A ltera's general-purpose Classic EPLDs M ultiple design entry m ethods LogiCaps schem atic capture


    OCR Scan     		PDF 44-Mbyte, 386-based truth table for ic 74138 16CUDSLR ALU IC 74183 IC 74151 diagram and truth table 74183 alu 74147 pin diagram and truth table pin diagram of IC 74184 HP-7475A 7408 ic truth table IC 74373 truth table

    P6102

    Abstract: EP6101-10
    Text: Classic EPLD Family J a n u ary 1998. v er. J Features Data S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith advanced, non-volatile


    OCR Scan     		PDF

    EP910

    Abstract: No abstract text available
    Text: EP910 EPLDs 'A Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ High-density replacement for TTL and 74HC with up to 900 gates High-performance 24-macrocell EPLD with tPD = 25 ns and counter frequencies up to 40 MHz Zero-power operation 20 (iA standby


    OCR Scan     		PDF EP910 24-macrocell

    EP1830

    Abstract: EP1810 jedec 74HC EP1810 EP18302 EP1830 jedec
    Text: EP1810 EPLDs High-Performance 48-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ Q General Description The EP1810 Erasable Programmable Logic Devices EPLDs offer LSI density,TTL-equivalentspeed, and low power consumption. Each EPLD can


    OCR Scan     		PDF EP1810 48-Macrocell EP1830-20, EP1830-25, EP1830-30 EP1830-25 EP1830 EP1810 jedec 74HC EP18302 EP1830 jedec

    Untitled

    Abstract: No abstract text available
    Text: EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 Features □ □ □ □ □ □ □ □ □ □ General Description A ltera's EP610 Erasable Programmable Logic Devices EPLDs can implement up to 600 equivalent gates of SSI and MSI logic functions in


    OCR Scan     		PDF EP610 16-Macrocell 24-pin, 300-mil 28-pin 20P610