Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    ALTED001 Search Results

    ALTED001 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    EPLD 5128

    Abstract: EPM5128-1 K942
    Text: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over


    OCR Scan     		PDF EPM5128 128-macrocell, 68-pin ALTED001 EPLD 5128 EPM5128-1 K942

    EPM5130

    Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
    Text: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture


    OCR Scan     		PDF EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin in100-Pin ALTED001 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130

    epf8282 hardware

    Abstract: No abstract text available
    Text: Configuration EPROMs ÆQn=^ for FLEX 8000 Devices - 1 Data Sheet August 1993, ver. 2 Features □ □ □ □ □ □ Functional Description Fam ily of serial EPROM s designed to configure FLEX 8000 devices


    OCR Scan     		PDF 20-pin 32-pin EPC1213, 800-EPLD. ALTED001 epf8282 hardware

    EP910T

    Abstract: altera EP910 EP910-T
    Text: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910


    OCR Scan     		PDF EP910T 24-macrocell EP910 EP910A 44-pin 40-pin ALTED001 altera EP910 EP910-T

    EP1810-35T

    Abstract: ALTERA EP altera EP1810
    Text: Features □ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20 ns, 25 ns, and 35 ns - Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs


    OCR Scan     		PDF 48-macrocell EP1810 MIL-STD-883-compliant 68-pin EP1810T EP1810-20T, EP1810-25T, EP1810-35T ALTED001 ALTERA EP altera EP1810

    J-Lead, QFP ceramic

    Abstract: PQFP 176 J-Lead
    Text: EPM5192A EPLD □ Features □ □ Preliminary Information □ □ □ High-performance, second-generation MAX 5000 EPLD developed on an advanced 0.65-m icron CM OS EPROM process High-speed upgrade for existing EPM 5192 designs High-speed multi-LAB architecture


    OCR Scan     		PDF EPM5192A 74-series 84-pin 100-Pin ALTED001 J-Lead, QFP ceramic PQFP 176 J-Lead

    EPM5192LC

    Abstract: ALTERA MAX 5000
    Text: MPLDs Mask-Programmed Logic Devices August 1993, ver. 2 Features Data Sheet □ □ □ □ □ □ □ □ □ General Description Masked versions of Altera programmable logic devices Reduced cost for high-volume production Available for high-density MAX 5000 devices, MAX 7000 devices, and


    OCR Scan     		PDF ALTED001 EPM5192LC ALTERA MAX 5000

    EPLD

    Abstract: No abstract text available
    Text: EPS464 EPLD Overview Features For detailed inform ation, refer to “ EPS464 EPLD” in this data sheet. □ □ □ □ □ High-performance, globally-routed, general-purpose EPLD Combinatorial speeds as fast as 20 ns Counter frequencies up to 67 MHz Pipelined data rates up to 71 MHz


    OCR Scan     		PDF EPS464 250-m 44-pin ALTED001 EPLD

    program EPM5032

    Abstract: EPLD 5032 VC 5032
    Text: EPM 5032 EPLD Features □ H ig h -sp eed , sin gle-L A B M A X 5000 E PL D t PD as fast as 15 ns C ou n ter frequ en cies up to 77 M H z P ip elined d ata rates up to 83 M H z 32 in d iv id u ally con fig u rab le m acrocells 64 sh areab le exp an d er p ro d u ct term s "e x p a n d e rs " allo w in g 68


    OCR Scan     		PDF EPM5032 -883-C -883-com ALTED001 program EPM5032 EPLD 5032 VC 5032

    EPM5064

    Abstract: EPM5064-1
    Text: EPM5064 EPLD Features □ □ □ □ □ □ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tPD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 63 MHz 128 shareable expander product terms "expanders" allowing over


    OCR Scan     		PDF EPM5064 64-macrocell, 44-pin EPS464 ALTED001 EPM5064-1

    epf8282 hardware

    Abstract: epf8282 block pf815 EPF81188 PF8150 EPF8282
    Text: FLEX 8000 Programmable Logic Device Family Datasheet August 1993, ver. 3 Features □ □ □ □ □ □ □ □ □ □ □ □ High-density, register-rich programmable logic device family 2,500 to 24,000 usable gates 282 to 2,252 registers Fabricated on a 0.8-m icron CM OS SRAM technology


    OCR Scan     		PDF ALTED001 epf8282 hardware epf8282 block pf815 EPF81188 PF8150 EPF8282

    48-MACROCELL

    Abstract: No abstract text available
    Text: EP1810 EPLD Features ^ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20,25,35, and 45 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs Pin-, function-, and programming file-compatible with Altera's


    OCR Scan     		PDF EP1810 48-macrocell EP1810T MIL-STD-883-compliant 68-pin ALTED001

    ALTERA EP610

    Abstract: MIL-STD-883-compliant
    Text: EP610 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 35 ns Counter frequencies up to 28.5 MHz Pipelined data rates up to 37 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		PDF EP610 MIL-STD-883-Compliant 16-macrocell 24-pin 16-bit MIL-STD-883-Compliant ALTERA EP610

    Altera EP1810

    Abstract: MIL-STD-883-compliant
    Text: EP1810 MIL-STD-883-Compliant EPLD Features □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 45 ns Counter frequencies up to 22.2 MHz Pipelined data rates up to 33.3 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		PDF EP1810 MIL-STD-883-Compliant 48-macrocell EP1810T 68-pin ALTED001 Altera EP1810

    QFP-2322

    Abstract: No abstract text available
    Text: EP M 7096 EPLD □ Features □ □ □ Preliminary Information □ □ High-density, erasable CMOS EPLD based on second-generation MAX architecture 1,800 usable gates Combinatorial speeds with tPD = 7.5 ns Counter frequencies up to 125 MHz Advanced 0.8-micron CMOS EEPROM technology


    OCR Scan     		PDF 84-pin 100-pin EPM7096 68-Pin ALTED001 QFP-2322

    Untitled

    Abstract: No abstract text available
    Text: EPM 7032-15T EPLD Features Low-cost version of the EPM7032. See "E PM 7032" in this data sheet for more information. High perform ance 32-m acrocell EPLD Combinatorial speeds with tPD = 15ns. Counter frequency as high as 76.9 MHz Pin, function, and programming-file com patible with the EPM7032.


    OCR Scan     		PDF 7032-15T EPM7032. 16-bit 7032-15T ALTED001

    ep330

    Abstract: vhdl code for 4 bit counter vhdl code for sr flipflop EP610 ORDERING EPLD 900
    Text: Classic Programmable Logic Device Family Data Sheet August 1993, ver. 1 □ Features □ □ □ □ □ □ □ □ □ Complete EPLD fam ily with logic densities up to 1,800 available gates 900 usable gates . See Table 1. M ultiple 20-pin PAL and GAL replacem ent and integration


    OCR Scan     		PDF 20-pin ALTED001 ep330 vhdl code for 4 bit counter vhdl code for sr flipflop EP610 ORDERING EPLD 900

    ALTERA MAX 5000 programming

    Abstract: No abstract text available
    Text: EPM 5016 EPLD Features □ □ □ □ □ □ High-speed, single-LAB M AX 5000 EPLD tPD as fast as 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells 32 shareable expander product terms "expand ers" allow ing 36


    OCR Scan     		PDF 24-mA EPM5016 16-bit EPM5016-15, EPM5016-17, EPM5016-20 ALTED001 ALTERA MAX 5000 programming

    Untitled

    Abstract: No abstract text available
    Text: Micro Channel EPLD User-Configurable Micro Channel Interface August 1993, ver. 2 Features Data Sheet □ □ □ □ □ 100% Micro Channel-compatible architecture eliminates design debug problems and allows faster board design time. 30-mA power-supply current conserves limited board power for


    OCR Scan     		PDF 30-mA 25-ns TED001 63111reS 24-mA ALTED001

    epm7032v

    Abstract: No abstract text available
    Text: Features. □ □ Preliminary Information □ □ □ □ □ 3.3-V version of the popular EPM7032 EPLD Combinatorial speeds with tPD = 12 ns Clock frequencies up to 90.9 M Hz Innovative pow er-saving features 30% to 50% pow er savings over 5-V operation Power-down m ode controlled by a pow er-down pin to allow


    OCR Scan     		PDF EPM7032 032V-12, 032V-15, 032V-20 ALTED001 epm7032v

    ATIC 64 C1

    Abstract: No abstract text available
    Text: EPS464 EPLD □ High-performance, globally-routed, general-purpose EPLD Combinatorial speeds as fast as 20 ns Counter frequencies up to 67 MHz Pipelined data rates up to 71 MHz 64 enhanced m acrocells and 256 shared expander product terms "exp an d ers" ; ideal for custom w aveform generation and state


    OCR Scan     		PDF EPS464 250-m EPS464-20, EPS464-25 ALTED001 ATIC 64 C1

    EP910

    Abstract: ep910-30
    Text: EP910 EPLD Features □ □ □ □ □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30,35, and 40 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs


    OCR Scan     		PDF EP910 24-macrocell EP910A EP910T 44-pin 40-pin 24-bit EP910-30, EP910-35, ep910-30

    epm7192

    Abstract: epm7192 packages 160-Pin PGA rop 101 3 PM 6 EPM7192-1
    Text: E P M 7192 E P LD Features □ □ □ □ □ H igh-d ensity, erasable C M O S E PL D based on second -generation M A X architectu re 3,750 u sable gates C om bin atorial speed s w ith t PD = 12 ns C o u n ter frequ en cies up to 90.9 M H z A d v an ced 0.8-m icro n C M O S E E P R O M tech nolog y


    OCR Scan     		PDF 160-pin EPM7192 ALTED001 epm7192 packages 160-Pin PGA rop 101 3 PM 6 EPM7192-1

    EP330

    Abstract: Altera ep330 AM 16v8 PAL AM 16v8 EP330-15
    Text: EP330 EPLD Features □ □ □ □ High-performance, 8-m acrocell Classic EPLD Combinatorial speeds with tPD = 12 ns Counter frequencies up to 100 MHz Pipelined data rates up to 125 MHz Low power; Ic c = 45 mA typical M acrocell flipflops can be individually programmed for registered or


    OCR Scan     		PDF EP330 20-pin, 20-pin EP330-12, EP330-15 EP330-15 ALTED001 Altera ep330 AM 16v8 PAL AM 16v8