9214a
Abstract: No abstract text available
Text: Preliminary Data Sheet August 2002 L9214A/G Low-Cost Ringing SLIC Introduction Applications The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line
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L9214A/G
L9214
GR-909
Sys17
DS01-144ALC
DS00-342ALC)
9214a
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l9214
Abstract: GR-909 L9214A L9214G MO-220 T7504 T8536 rgn 1064 agere 840
Text: Preliminary Data Sheet October 2001 L9214A/G Low-Cost Ringing SLIC Introduction Applications The Agere Systems Inc. L9214 is a subscriber line interface circuit that is optimized to provide a very low-cost solution for short- and medium-loop applications. This device provides the complete set of line
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L9214A/G
L9214
GR-909
DS01-144ALC
DS00-342ALC)
L9214A
L9214G
MO-220
T7504
T8536
rgn 1064
agere 840
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TMPRFE2G5
Abstract: MARS2G5 bey34 DIODE BA40 LVTTL25
Text: Hardware Design Guide September 8, 2004 MARS2G5 P-VC-XTRM TMPRFE2G5 Datamapper 2488/622/155 Mbits/s SONET/SDH x 10/100/1000 Mbits/s Ethernet 1 Introduction The documentation package for the Datamapper device consists of the following documents, available on a password protected website:
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DS04-011MPIC
TMPRFE2G5
MARS2G5
bey34
DIODE BA40
LVTTL25
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LSP2908
Abstract: agere 840
Text: a8e re AdLib systems OCR Evaluation Advance Data Sheet September 2001 LSP2908 8-Channel, High-Voltage Driver Features . Eight amplifier channels in one package . Outputs from -298 V to +160 V per channel . Programmable output current limit 100 pA to 500 j A
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LSP2908
LSP2908
DS01-095ASP
agere 840
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LCK4801
Abstract: LCK4802 MPC998
Text: Advance Data Sheet December 2001 LCK4802 Low-Voltage PECL Differential Clock General Features The LCK4802 is a low-voltage, 3.3 V PECL differential clock synthesizer. The LCK4802 supports two differential PECL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to
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LCK4802
LCK4802
DS02-070HSI
DS01-265HSI)
LCK4801
MPC998
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LCK4801
Abstract: MPC998 2274a
Text: Preliminary Data Sheet December 2001 LCK4801 Low-Voltage HSTL Differential Clock General Features The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to
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LCK4801
LCK4801
DS02-069HSI
DS01-234HSI)
MPC998
2274a
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M-LSP2908
Abstract: LSP2908
Text: Advance Data Sheet September 2001 LSP2908 8-Channel, High-Voltage Driver Features • Eight amplifier channels in one package ■ Outputs from –298 V to +160 V per channel ■ ■ condition that |VHP – VHN| ≤ 300 V. Voltage gain is set by external resistors. Each amplifier can output
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LSP2908
LSP2908
DS01-095ASP
M-LSP2908
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7495 data sheet
Abstract: LCK4801
Text: Preliminary Data Sheet July 2001 LCK4801 Low-Voltage HSTL Differential Clock General Features The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to
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LCK4801
LCK4801
DS01-234HSI
7495 data sheet
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gtx2 0135
Abstract: No abstract text available
Text: Preliminary Data Sheet May 2002 T8533/T8534 Quad Programmable Codec and Echo Canceller Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant
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T8533/T8534
64-tap
DS02-270ALC
DS01-250ALC)
gtx2 0135
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25D30
Abstract: No abstract text available
Text: Data Sheet July 2002 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame
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T8535B/T8536B
DS02-339ALC
DS02-042ALC)
25D30
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parabolic antenna
Abstract: LNA x-band 8910A 302opt apc back-ups 500 rs apc back-ups 800 rs diagram X-band lna hpa L-band
Text: Data Sheet, Rev. 1 September 2001 System 8000 Fiber-Optic Interfacility Links Description Designed to interface directly with earth station equipment, the multifaceted System 8000 interfacitlity link offers a wide variety of unique, site-specific interconnectivity solutions for
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RS-232
RS-485
RS-422
the12-4106)
DS00-302OPTO-1
DS00-302OPTO)
parabolic antenna
LNA x-band
8910A
302opt
apc back-ups 500 rs
apc back-ups 800 rs diagram
X-band lna
hpa L-band
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PUB43801
Abstract: T5504 T7504
Text: Data Sheet February 2002 T7504 and T5504 Quad PCM Codecs with Filters Features Description • 5 V only ■ Low-power, latch-up-free CMOS technology — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation ■ Automatic master clock frequency selection
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T7504
T5504
DS02-149ALC
DS99-201ALC)
PUB43801
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pin diagram of ic 7495
Abstract: data sheet ic 7495 pin diagram of ic 7495 A pin diagram of ic 7495 pin diagram data sheet of ic 7495 ALL DATA SHEET ic 7495 shift registers 7495 data sheet pin diagram of ic 555 pin diagram of 7495
Text: Preliminary Data Sheet July 2001 T8533/34 Quad Programmable Line Card Signal Processor Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant
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T8533/34
64-tap
DS01-250ALC
DS01-058ALC)
pin diagram of ic 7495
data sheet ic 7495
pin diagram of ic 7495 A
pin diagram of ic 7495 pin diagram
data sheet of ic 7495
ALL DATA SHEET
ic 7495 shift registers
7495 data sheet
pin diagram of ic 555
pin diagram of 7495
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NEC Technologies
Abstract: No abstract text available
Text: Data Sheet November 2006 USS2000 Four-Port USB2.0 PCI-to-USB Host Controller 1 Features 2 Applications 32-bit, 33 MHz PCI interface compliant with PCI Local Bus Specification Revision 2.2. Seamless integration with 3 V or 5 V PCI-based computer products.
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USS2000
32-bit,
DS06-009CMPR-1
DS06-008CMPR)
NEC Technologies
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Untitled
Abstract: No abstract text available
Text: Preliminary Data Sheet August 2002 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame
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T8538B
DS02-345ALC
DS01-280ALC)
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EC60825-1
Abstract: EC60825 TD1611 STM-16 TD16L1 agilent receiver OC-48 1EC60825-1 transmitter agilent oc 192 agere 840 demultiplexer outline
Text: a8e re AdLib OCR Evaluation systems Advance Data Sheet May 2002 TD16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer Description The TD16-type transponder performs straightforward, bit-level parallel-to-serial converting in the
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TD16-Type
16-Channel
16-bit,
DS02-249TPDR
DS01-240PTO)
EC60825-1
EC60825
TD1611
STM-16
TD16L1
agilent receiver OC-48
1EC60825-1
transmitter agilent oc 192
agere 840
demultiplexer outline
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Agere read channel
Abstract: DATA Sheet IC 555 84 PLCC pin configuration data sheet book ic 555 Ringing Subscriber Line Interface Circuit NXP T8533 T8534 T8535B T8536B T8538B
Text: Preliminary Data Sheet September 2001 T8535B/T8536B Quad Programmable Codec Features • 5 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame
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T8535B/T8536B
Differe610-712-4106)
DS01-315ALC
DS01-251ALC)
Agere read channel
DATA Sheet IC 555
84 PLCC pin configuration
data sheet book ic 555
Ringing Subscriber Line Interface Circuit NXP
T8533
T8534
T8535B
T8536B
T8538B
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ECHO canceller IC
Abstract: L7591 L9215G T8534
Text: Preliminary Data Sheet April 2002 T8534 Quad Programmable Codec and Echo Canceller Features • ■ Includes codec, termination impedance, and echo canceller in one device for line card applications Programmable µ-law, linear, or A-law PCM input and output ITU-T G.712 compliant
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T8534
64-tap
DS02-205ALC
ECHO canceller IC
L7591
L9215G
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8503
Abstract: CA 3140 OP AMP PUB43801 T8502 T8503
Text: Data Sheet February 2002 T8502 and T8503 Dual PCM Codecs with Filters Features • +5 V only ■ Two independent channels ■ Pin-selectable receive gain control ■ Pin-selectable µ-law or A-law companding ■ Automatic powerdown mode ■ Low-power, latch-up-free CMOS technology
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T8502
T8503
DS02-151ALC
DS98-342ALC
8503
CA 3140 OP AMP
PUB43801
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LCK4802
Abstract: BA 658 pll 564
Text: Preliminary Data Sheet July 2001 LCK4802 Low-Voltage PECL Differential Clock General Features The LCK4802 is a low-voltage, 3.3 V PECL differential clock synthesizer. The LCK4802 supports two differential PECL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to
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LCK4802
LCK4802
DS01-265HSI
BA 658
pll 564
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Untitled
Abstract: No abstract text available
Text: Data Sheet May 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Interface Features 1394a-2000 OHCI link and PHY core function in a single device: — 100-pin TQFP package also available in a leadfree package; see ordering information on page 85.
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FW322
1394a-2000
100-pin
DS04-179CMPR
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FW3227
Abstract: No abstract text available
Text: Data Sheet November 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Features supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic — Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders — While unpowered and connected to the bus, will
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FW322
1394a-2000
100-pin
DS05-030CMPR
DS04-179CMPR)
FW3227
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L7583
Abstract: L7583B L8567 T7507 pub 43801
Text: Data Sheet August 1999 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance Features • 5 V only ■ Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation
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T7507
DS99-273ALC
DS99-080ALC)
L7583
L7583B
L8567
pub 43801
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data sheet ic 7495
Abstract: gtx2 0135 0124C 7495 ic data sheet DATA Sheet IC 555 digital clock ckt diagram ic 7495 data sheet pin diagram of ic 7495 pin diagram of ic 7495 A Ringing Subscriber Line Interface Circuit NXP
Text: Preliminary Data Sheet May 2001 T8538B Quad Programmable Codec Features • 3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes: — Up to 256 time slots per frame
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T8538B
DS01-205ALC
data sheet ic 7495
gtx2 0135
0124C
7495 ic data sheet
DATA Sheet IC 555
digital clock ckt diagram
ic 7495 data sheet
pin diagram of ic 7495
pin diagram of ic 7495 A
Ringing Subscriber Line Interface Circuit NXP
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