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    ADDRESS SWITCH Search Results

    ADDRESS SWITCH Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TBAW56 Toshiba Electronic Devices & Storage Corporation Switching Diode, 80 V, 0.215 A, SOT23 Visit Toshiba Electronic Devices & Storage Corporation
    HN1D05FE Toshiba Electronic Devices & Storage Corporation Switching Diode, 400 V, 0.1 A, ES6 Visit Toshiba Electronic Devices & Storage Corporation
    74HC4053FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SPDT(1:2)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    AM25LS2548DM/R Rochester Electronics LLC AM25LS2548 - Chip Select Address Decoder with Acknowledge Visit Rochester Electronics LLC Buy
    54LS259B/BEA Rochester Electronics LLC 54LS259 - LATCH, 8-Bit ADDRESSABLE - Dual marked (M38510/31605BEA) Visit Rochester Electronics LLC Buy

    ADDRESS SWITCH Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    nec 2501

    Abstract: 8 bit binary full adder address generation unit DSP56K 16 bit full adder
    Text: SECTION 4 ADDRESS GENERATION UNIT MOTOROLA ADDRESS GENERATION UNIT 4-1 SECTION CONTENTS SECTION 4.1 ADDRESS GENERATION UNIT AND ADDRESSING MODES .3 SECTION 4.2 AGU ARCHITECTURE .3 4.2.1 Address Register Files Rn .3


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: Advance Information Synch. MROM KM23SV64205T 2Mx32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 x32 : CA0 ~ CA8 (x16)


    Original     		PDF KM23SV64205T 2Mx32 33MHz 50MHz 66MHz 83MHz 100MHz 50MHz 86-TSOP2-400)

    KM23SV64205T-10

    Abstract: KM23SV64205T-12 KM23SV64205T-20 RA12
    Text: Advance Information Synch. MROM KM23SV64205T 2Mx32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 x32 : CA0 ~ CA8 (x16)


    Original     		PDF KM23SV64205T 2Mx32 33MHz 50MHz 66MHz 83MHz 100MHz 50MHz KM23SV64205T-10 KM23SV64205T-12 KM23SV64205T-20 RA12

    Untitled

    Abstract: No abstract text available
    Text: Advance Information Synch. MROM K3S7V2000M-TC 2Mx32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 x32 : CA0 ~ CA8 (x16)


    Original     		PDF K3S7V2000M-TC 2Mx32 33MHz 50MHz 66MHz 83MHz 100MHz 50MHz

    K3S7V2000M-TC

    Abstract: K3S7V2000M-TC10 K3S7V2000M-TC12 K3S7V2000M-TC15 K3S7V2000M-TC20 K3S7V2000M-TC30 RA12
    Text: K3S7V2000M-TC Synch. MROM 64M-Bit 4Mx16 /2Mx32 Synchronous MASKROM FEATURES GENERAL DESCRIPTION • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Address: Row address: RA0 ~ RA12 Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16)


    Original     		PDF K3S7V2000M-TC 64M-Bit 4Mx16 /2Mx32) 33MHz 50MHz 66MHz 83MHz 100MHz K3S7V2000M-TC K3S7V2000M-TC10 K3S7V2000M-TC12 K3S7V2000M-TC15 K3S7V2000M-TC20 K3S7V2000M-TC30 RA12

    multiplexing demultiplexing in microcontroller

    Abstract: 80C196KD F-100 UT54ACS373 UT80CXX196KD
    Text: UTMC Application Note UT80CXX196KD MicroController JD02* ALE Considerations Introduction: The UT80CXX196KD microcontroller incorporates a multiplexed address and data bus. As a result, the microcontroller provides an Address Latch Enable (ALE) signal to clock an external address latch. The address latch is used to


    Original     		PDF UT80CXX196KD UT54ACS373 AD15-AD8 A15-A8 UT80CXX196KD multiplexing demultiplexing in microcontroller 80C196KD F-100 UT54ACS373

    Untitled

    Abstract: No abstract text available
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x 8 TIMEKEEPER SRAM WITH ADDRESS/ADDRESS/DATA MULTIPLEXED FEATURES SUMMARY • SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER ■ ■ ■ REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED I/O PINS


    Original     		PDF M48T559Y 28-pin M48T59 M48T559Y: 28-LEAD

    M48T559Y

    Abstract: M48T59 M4T28-BR12SH SOH28
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x 8 TIMEKEEPER SRAM WITH ADDRESS/ADDRESS/DATA MULTIPLEXED FEATURES SUMMARY • SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER ■ REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ■ ADDRESS/ADDRESS/DATA MULTIPLEXED ■ I/O PINS


    Original     		PDF M48T559Y M48T59 28-pin SOH28 M48T559Y M48T59 M4T28-BR12SH SOH28

    M48T559Y

    Abstract: M48T59 M4T28-BR12SH SOH28
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x 8 TIMEKEEPER SRAM WITH ADDRESS/ADDRESS/DATA MULTIPLEXED FEATURES SUMMARY • SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER ■ ■ ■ REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED I/O PINS


    Original     		PDF M48T559Y M48T59 28-pin M48T559Y M48T59 M4T28-BR12SH SOH28

    DS1217M

    Abstract: DS1222 DS1217
    Text: DS1217M DS1217M Nonvolatile Read/Write Cartridge FEATURES PIN ASSIGNMENT • User-insertable Name • Data retention greater than 5 years Position Name Ground A1 B1 No Connect +5 Volts A2 B2 Address 14 Write Enable A3 B3 Address 12 Address 13 A4 B4 Address 7


    Original     		PDF DS1217M DS1217M 100pF DS1222 DS1217

    Untitled

    Abstract: No abstract text available
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x8 TIMEKEEPER SRAM with Address/Address/Data Multiplexed FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED


    Original     		PDF M48T559Y M48T59 M48T559Y: 28-LEAD

    M48T559Y

    Abstract: M48T59 M4T28-BR12SH SOH28
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x8 TIMEKEEPER SRAM with Address/Address/Data Multiplexed FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED


    Original     		PDF M48T559Y M48T59 M48T559Y: 28-LEAD M48T559Y M48T59 M4T28-BR12SH SOH28

    00FF2000

    Abstract: No abstract text available
    Text: APPLICATION NOTE H8SX Family 8-Bit Absolute Address Space Switching Introduction With an H8SX CPU, any 8-bit absolute address space is selectable as desired. For all CPUs of the conventional H8S Family, the 8-bit absolute address space is fixed to the range from H’FFFF00 to


    Original     		PDF FFFF00 256-byte REJ06B0647-0100/Rev 00FF2000

    Untitled

    Abstract: No abstract text available
    Text: M48T559Y 5.0V, 64 Kbit 8 Kbit x8 TIMEKEEPER SRAM with Address/Address/Data Multiplexed FEATURES SUMMARY • SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ADDRESS/ADDRESS/DATA MULTIPLEXED I/O PINS WATCHDOG TIMER - MONITORS OUT-OFCONTROL PROCESSOR OR “HUNG” BUS


    Original     		PDF M48T559Y M48T59

    L7 diode

    Abstract: transistor DAG ADSP-21000
    Text: Data Addressing 4.1 4 OVERVIEW The ADSP-2106x’s two data address generators DAGs simplify the task of organizing data by maintaining pointers into memory. The DAGs allow the processor to address memory indirectly; that is, an instruction specifies a DAG register containing an address instead of the address value itself.


    Original     		PDF ADSP-2106x 32-bit 24-bit ADSP-21000 L7 diode transistor DAG ADSP-21000

    MCF54452

    Abstract: M5445EVB JP912 MCF54450 MCF54454 MCF54455 hyperterminal 0x80000000-0x8FFFFFFF i phone 4 pin map MCF54453
    Text: ColdFire MCF5445x Internal Peripheral Space Memory Map MCF5445x Family Configurations Base Address Slot # Internal Address[31:28] Address Range Destination Slave Slave Memory Size 0xFC00_0000 SCM MPR and PACRs 00xx 0x0000_0000–0x3FFF_FFFF FlexBus 1024 MB


    Original     		PDF MCF5445x MCF5445x 0xFC00 0x0000 0x4000 0x8000 0xFC03 0x9000 MCF54452 M5445EVB JP912 MCF54450 MCF54454 MCF54455 hyperterminal 0x80000000-0x8FFFFFFF i phone 4 pin map MCF54453

    Untitled

    Abstract: No abstract text available
    Text: SYM92C500 GLOSSARY ALB: Address Lookup Bus A bus defined in the switched bus system that carries address and forwarding information between port devices. ALI: Address Lookup Interface The signals on the SYM92C500 that connect to and support the Address Lookup Bus.


    OCR Scan     		PDF SYM92C500

    DS1217

    Abstract: tda 2261 DS1217A DS1640
    Text: DS1217A DALLAS SEMICONDUCTOR D S 1217A Nonvolatile R ead/W rite C artridge FEATURES PIN ASSIGNMENT • User-insertable Name Position Name Ground A1 — B1 +5 Volts A2 B2 Address 14 Write Enable A3 B3 Address 12 Address 13 A4 B4 Address 7 Address 8 A5 B5 Address 6


    OCR Scan     		PDF DS1217A 28-pin DS1217 2Kx8to32Kx8 tda 2261 DS1640

    DS1217

    Abstract: DS1666 DS2011D DS1217A DS1000M DS1868 1217A DS1640
    Text: D S 1217A DALLAS SEMICONDUCTOR D S 1217A Nonvolatile R ead/W rite C artridge FEATURES PIN ASSIGNMENT • User-insertable Name Position Name Ground A1 — B1 +5 Volts A2 B2 Address 14 Write Enable A3 B3 Address 12 Address 13 A4 B4 Address 7 Address 8 A5 B5


    OCR Scan     		PDF DS1217A 28-pin DS1217 2Kx8to32Kx8 DS1666 DS2011D DS1217A DS1000M DS1868 1217A DS1640

    tc001

    Abstract: Am2940
    Text: Am2940 DMA Address Generator DISTINCTIVE CHARACTERISTICS DMA Address Generation Programmable Control Modes Generates memory address, word count and DONE signal for DMA transfer operation. Provides four types of DMA transfer control plus memory address increm ent/decrem ent.


    OCR Scan     		PDF Am2940 Am2940 03575B tc001

    FTC 5277

    Abstract: FTC 5278 Am2940
    Text: Am 2940 DMA Address Generator DISTINCTIVE CHARACTERISTICS DMA Address Generation Generates memory address, word count and DONE signal for DMA transfer operation. Expandable Eight-bit Slice Any number of Am2940's can be cascaded to form larger memory addresses - three devices address 16


    OCR Scan     		PDF Am2940 03575B FTC 5277 FTC 5278

    Untitled

    Abstract: No abstract text available
    Text: 28F016SA The BYTE# pin allows either x8 or x16 read/writes to the 28F016SA. BYTE# at logic low selects 8-bit mode with address Ao selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address Ai becoming the lowest order address and address


    OCR Scan     		PDF 28F016SA 28F016SA. 16-bit 28F016SA 28F008SA 28F008SA-based 16-Mbit

    74F547

    Abstract: transaprent
    Text: FAST 74F547 Decoder/Demultiplexer FAST Products Octal Decoder/Demultiplexer With Address Latches And Acknowledge Open Collector Product Specification FEATURES • 3-to-8 line address decoder • Address storage latches TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT


    OCR Scan     		PDF 74F547 N74F547N N74F547D 20-Pin 74F547 500ns transaprent

    AM2911

    Abstract: No abstract text available
    Text: VU862WV Am29811A Next Address Control Unit DISTINCTIVE CHARACTERISTICS Next address control unit for the Am2911A Micropro­ gram Sequencer 16 next address instructions Test input tor conditional instructions Separate outputs to control the Am2911A, an indepen­


    OCR Scan     		PDF VU862WV Am29811A Am2911A 3649A VU86ZU1V AM2911